Browse Prior Art Database

BiCMOS DRIVER WITH LATCH

IP.com Disclosure Number: IPCOM000006158D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2001-Dec-10
Document File: 1 page(s) / 48K

Publishing Venue

Motorola

Related People

Paul H. Hsueh: AUTHOR [+2]

Abstract

The purpose of this invention is to design a BiCMOS buffer with a latch function. This circuit allows us to accomplish at least two goals: (1) Improve read cycle time by cutting data flow pipe (2) Implement multi-pipe-lined architecture.

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MOTDROLA INC. Technical Developments Volume 12 April 1991

BiCMOS DRIVER WITH LATCH~

by Paul H. Hsueh and Douglas D. Smith

  The purpose of this invention is to design a BiCMOS buffer with a latch function. This circuit allows us to accomplish at least two goals:

(1) Improve read cycle time by cutting data flow pipe
(2) Implement multi-pipe-lined architecture.

Referring to the Figure, there are four main blocks which can be identified:

Block 1 which includes 113, 131, P6, N54, N66 and N57 and allows for BiCMOS buffer capability;

Block 2 which includes P34, N32 and N47 and allows for tri-state capability;

Block 3 which includes P40, P23, P38, N35, N27


and N60 and forms a dynamic latch; and

  Block 4 which includes P56 and N41 and forms a CMOS inverter for generating complementary clock signals in order to enable or tri-state the BiCMOS buffer.

  Briefly, when elk is high, Block 2 is acting as a passing gate to enable the BiCMOS buffer. When the BiCMOS buffer is enabled, the dynamic latch is shut off in order to reduce the output impedance and increase the output drive. On the other hand, when elk is low, Block 2 isiacting as a disable gate for turning off both of the totem-pole pair of bipolar transistors. This is indicative of a "tri-state" condition. By turning on the dynamic latch, data will be kept at the outout of the circuit.

'Cin=6.ElfF

*Cin=19.5fF

178

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