Browse Prior Art Database

RING-OSCILLATOR PLL PHASE SELECTORS

IP.com Disclosure Number: IPCOM000006164D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-10
Document File: 3 page(s) / 107K

Publishing Venue

Motorola

Related People

Shawn R. McCaslin: AUTHOR [+2]

Abstract

This paper includes hvo different phase selectors that allow high-resolution selection of clock phase from a ring oscillator, one which uses minimum hardware, and one which provides minimum phase variation. Although the idea of using a ring oscillator PLL to provide high-resolution control of clock phase is not new, we believe that o;r explicit description of the logic required to implement the required control is new.

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MOTOROLA INC. Technical Developments Volume 13 July 1991

RING-OSCILLATOR PLL PHASE SELECTORS

by Shawn R. McCaslin and Steve Cozart

ABSTRACT

  This paper includes hvo different phase selectors that allow high-resolution selection of clock phase from a ring oscillator, one which uses minimum hardware, and one which provides minimum phase variation. Although the idea of using a ring oscillator PLL to provide high-resolution control of clock phase is not new, we believe that o;r explicit description of the logic required to implement the required control is new.

INTRODUCTION

A ring-oscillator PLL consists of a phase detector,

a loop filter, and a VCO. The VCO consists of an odd number of inverters in a ring, where the output fre- quency is normally controlled by the supply current of the inverters (see Figure 1). This control is possible for HCMOS, since the propagation time through an inverter decreases with increasing supply current, so the frequency of the square wave that propagates around the loop increases with the supply current.

  One application of a ring oscillator is to provide improved phase resolution of the input clock signal. In particular, for n inverter stages, the phase delay

across an inverter would be 2x1211. Access to each inverter output would therefore allow the phase of the output clock from the PLL to be selectable to that resolution.

  As shown in Figure 1, the known PLL uses these high-resolution clock phases as part of a separate DPLL. That is, the ring-oscillator provides the high- resolution clock phases, and the DPLL selects the best phase according to some criteria not observable by the ring-oscillator PLL.

PURPOSE

  The purpose of this phase selector is to facilitate access and control of the output clock phase from an n-stage ring-oscillator PLL relative to t...