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A DUAL PASS SCAN MECHANISM FOR MINIMIZING SERIAL SCAN OUTPUTS

IP.com Disclosure Number: IPCOM000006165D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-10
Document File: 2 page(s) / 105K

Publishing Venue

Motorola

Related People

Eytan Hartung: AUTHOR [+3]

Abstract

Testability of microprocessors and peripherals which use structured designs such as PLAs and ROMs typically require controllability and observability of these types of designs. This criteria is especially needed in microprocessors where internal access is limited. This can be accomplished through a serial shifter path or so-called "scan path" to minimize the impact on silicon area. This testing methodology typically requires a master/slave type shifter bit or so called scan latch for every input for controllability and one for every output for observability. The procedure to access a given structure is described below.

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MOTOROLA INC. Technical Developments Volume 13 July 1991

A DUAL PASS SCAN MECHANISM FOR MINIMIZING SERIAL SCAN OUTPUTS

by Eytan Hartung, Mike Gladden and Oded Yishay

  Testability of microprocessors and peripherals which use structured designs such as PLAs and ROMs typically require controllability and observability of these types of designs. This criteria is especially needed in microprocessors where internal access is limited. This can be accomplished through a serial shifter path or so-called "scan path" to minimize the impact on silicon area. This testing methodology typically requires a master/slave type shifter bit or so called scan latch for every input for controllability and one for every output for observability. The procedure to access a given structure is described below.

1). Serial scan in the inputs to the circuit structure under test.
2). Activate circuit structure under test.
3). Serial scan out the outputs of the circuit structure under test.

  For structures such as ROMs which typically have hundreds of outputs depending on the complexity of the microprocessor, the test time and silicon impact is dominated mainly by the number of outputs of the circuit structure under test.

  This article describes a silicon efftcient serial scan latch and the test methodology to support it. To sup- port this new output scan latch a dual pass scanning technique is required to observe all the outputs of a given structure.

  This is accomplished by the duality of a single half latch flip-flop that typically already exits due to the need to latch the outputs of the structure in normal operation. Referencing Figure 1.0, this single half latch flip-flop serves as master or slave depending on which scan pass is performed. During the first pass, the odd numbered outputs are scanned out with the odd numbered scan latches serving as the master portion of the shifter and the even numbered output latches serving as the slave portion. During the second or final pass the even numbered outputs are

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scanned out with the even numbered output latches serving as the master portion of the shifter and the odd numbered output latches serving as the slave portion. This is accomplished by a unique clocking scheme in which the filtering of a master test clock is done to assign master OT slave properties to a single half latch flip-flop.

The procedure to access a given structure is described below.

1). Serial scan in the inputs to the circuit structure under test.
2). Activate circuit structur...