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COMBINATION PC/LINE PREFETCH ADDRESS ADDER

IP.com Disclosure Number: IPCOM000006168D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-11
Document File: 2 page(s) / 78K

Publishing Venue

Motorola

Related People

Thomas Spohrer: AUTHOR [+4]

Abstract

The pc section of the 68040 integer unit calculates the instruction program counter (PC) and instruction prefetch address (PFA). The PC is a word address (31-bits) and the prefetch address is a quad-word address (29-bits). In each cycle, the pc unit calculates a new PC based on the length of the dispatched instruction and PFA based on length of the dispatched instruction and the number of words left in the 128- bit, 8-word prefetch buffer, (PB).

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MOTOROLA INC. Technical Developments Volume 13 July 1991

COMBINATION PC/LINE PREFETCH ADDRESS ADDER

by Thomas Spohrer, Russell Reininger,

Jeffrey Freeman and Ashok Someshwar

  The pc section of the 68040 integer unit calculates the instruction program counter (PC) and instruction prefetch address (PFA). The PC is a word address (31-bits) and the prefetch address is a quad-word address (29-bits). In each cycle, the pc unit calculates a new PC based on the length of the dispatched instruction and PFA based on length of the dispatched instruction and the number of words left in the 128- bit, 8-word prefetch buffer, (PB).

  There exists a loose relationship between the PC and PFA such that the two addresses can be calculated with one 29-bit incrementer and a 3-bit adder saving a 28 bit incrementer.

The PC section of the 68040 integer unit is the section which calculates the PC and the prefetch

address. On a given cycle, three addresses need to be calculated: the PC if a branch is taken, the PC if a branch is not taken (the not-taken PC), and the cache half-line prefetch address of the next instruction (assuming no branch). There exists a relationship between the not-taken PC and the prefetch address. One adder which is split into hvo parts can be used to calculate both.

  The next cache half-line prefetch address is calcu- lated every cycle, but the prefetch address register is not updated with this value until the not-taken PC crosses a half-line boundary. Note that,...