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COMBINATION OF ALIGNMENTS AND REGISTRATION TARGETS

IP.com Disclosure Number: IPCOM000006199D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-13
Document File: 2 page(s) / 115K

Publishing Venue

Motorola

Related People

Whit G. Waldo: AUTHOR

Abstract

Overlay of integrated circuits refers to the spatial relationship of two levels in the stack that makes a cir- cuit functional. Generally, overlay is referenced by the current level being imaged, and then either etched or implanted, to a critical previous level. Device engi- neers determine which previous level is critical to attain functionality of the circuit. Overlay involves the coupling of critical dimension control of features on the two levels and the registration of the two levels. The paradigm in integrated circuit fabrication pro- cesses is to use an alignment target design recom- mended by the manufacturer to align the mask to the wafer and to use a separate registration structure to measure the success in alignment.

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MOTOROLA INC. Technical Developments \iolume 13 July 1991

COMBINATION OF ALIGNMENTS AND REGISTRATION TARGETS1

by Whit G. Waldo

  Overlay of integrated circuits refers to the spatial relationship of two levels in the stack that makes a cir- cuit functional. Generally, overlay is referenced by the current level being imaged, and then either etched or implanted, to a critical previous level. Device engi- neers determine which previous level is critical to attain functionality of the circuit. Overlay involves the coupling of critical dimension control of features on the two levels and the registration of the two levels. The paradigm in integrated circuit fabrication pro- cesses is to use an alignment target design recom- mended by the manufacturer to align the mask to the wafer and to use a separate registration structure to measure the success in alignment.

Alignment targets have taken many different

shapes including isolated features or arrays of long lines, small squares, chevrons, diamonds, brick pat- terns, etc. However the shape of the alignment target, their function is the same. Light illuminates the align- ment target on the wafer and is scattered off the edges. Alignment targets can be arranged in grating type structures. Light scattered by the various periodic SW- face features of a reflection grating will come off the target at specific, well-defined angles depending upon the grating construction and the alignment wave- length. This light can be collected for signal process- ing to find the target position. More generally, scan- ners and steppers collect the first or many of the diffracted orders in an attempt to locate the edges of the alignment targets. The information about the edges of the align targets is used to calculate the target center position.

  The quality of alignment is judged subjectively by visual analysis of overlay of features between different patterned levels using either optical microscopes or a scanning electron microscope. Objective analysis of alignment is accomplished with vernier patterns or with higher gauge capability using overlay measure- ment tools that compare patterns like a box-in-a box.

  Ideal registration of two levels would be as accu- rate as the CAD drawings!of the integrated circuit lev- els with no grid distortions or translations. The CAD information usually is s&red on computer tapes. In reality, the CAD drawing: of a level become distorted and translated from the!! ideal grid positions with wafer processing. The FAD drawings usually are used to make a mask so the mask's image can be trans- ferred somehow onto thk wafer to make the circuit level. A mask consists ~of transparent regions and opaque regions; opaque~regions block light that is used to expose photoresiit on a wafer to transfer the mask image. Electron bkam machines use the CAD tapes to write the pattern's of the circuit...