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SUMMARY OF TRENCH TOP SIDE SUBSTRATE CONTACT TECHNOLOGY-PROCESS TECHNIQUES FOR DOPING TRENCH FILL

IP.com Disclosure Number: IPCOM000006218D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-14
Document File: 3 page(s) / 108K

Publishing Venue

Motorola

Related People

Sam L. Sundaram: AUTHOR [+3]

Abstract

Substrate top side contact using deep trenches are becoming essential for high performance VLSI tech- nology. Top side contacts unlike conventional bottom substrate contacts should ease packaging constraints for multi-pin TAB and PGA (flip chip) high perfor- mance packages that are used in advanced ECL/BIC- MOS products. This also eases cooling issues for ECL products where the substrate is at -5.2V (electri- cal hazard). The deep narrow trenches used here as top side substrate contacts would form a solid ground between devices (better RF shield) and can be used for power/logic ICs. Being narrow trenches of submicron dimension, this approach would improve packaging density unlike diffused top side contacts. So the appli- cation of top side substrate contact is numerous encompassing ECL, BICMOS, Power ICs, Power hun- gry CMOS and ASIC products.

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MOTOROLA INC. Technical Developments Volume 13 July 1991

SUMMARY OF TRENCH TOP SIDE SUBSTRATE CONTACT TECHNOLOGY-PROCESS TECHNIQUES FOR DOPING TRENCH FILL

by Sam L. Sundaram, Juergen Foerstner and Peter Zdebel

  Substrate top side contact using deep trenches are becoming essential for high performance VLSI tech- nology. Top side contacts unlike conventional bottom substrate contacts should ease packaging constraints for multi-pin TAB and PGA (flip chip) high perfor- mance packages that are used in advanced ECL/BIC- MOS products. This also eases cooling issues for ECL products where the substrate is at -5.2V (electri- cal hazard). The deep narrow trenches used here as top side substrate contacts would form a solid ground between devices (better RF shield) and can be used for power/logic ICs. Being narrow trenches of submicron dimension, this approach would improve packaging density unlike diffused top side contacts. So the appli- cation of top side substrate contact is numerous encompassing ECL, BICMOS, Power ICs, Power hun- gry CMOS and ASIC products.

  In this summary, we have briefly outlined the pro- cess techniques developed to make top side substrate contact for MOSAIC 5 technology where the P-type substrate is moderately doped (lE17 cm-3). Essen- tially the top side contact is done through a conducting column filled from top to all the way down to sub- strate using submicron trenches. Also we have shown how to build trench capacitors using these deep trench

substrate contacts (spin-off).

  A method of producing dooed polvsilicon w ductine column) in deep narrow trenches where top side substrate contact is to be produced is discussed. The polysilicon fill makes the diffusion process option to dope the poly feasible for 5 micron deep trenches in a reasonable diffusion time and temperature (Dt prod- uct) that are critical for VLSI products. Basically the undoped poly fill inside the oxide lined (3) trenches

after planarization can be doped by a) Boron implant and diffuse, b) solid source deposition and diffusion using boron disc, c) Borosili...