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A NEW DESIGN APPROACH TO IMPROVE ACQUISITION TIME OF PHASE-LOCKED LOOP (pll) SYSTEMS

IP.com Disclosure Number: IPCOM000006222D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-14
Document File: 2 page(s) / 98K

Publishing Venue

Motorola

Related People

Ahmad Atriss: AUTHOR

Abstract

Abstract-This disclosure describes a new design approach being used in order to improve the pll acquisition (lock-in) time. A new circuit is added in order to initialize the loop filter node at a voltage level close to the center between VDD and VSS so that the lock-in (acquisition) time of the phase-locked loop system will have an improvement (reduction) of at least 10 times over present state of the art of HCMOS technology. The loop filter is a part of a high fre- quency phase locked loop system which is used as a part of a high performance data communication chip.

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MO7WROLA INC. Technical Developments Volume 13 July 1991

A NEW DESIGN APPROACH TO IMPROVE ACQUISITION TIME OF PHASE-LOCKED LOOP (~11) SYSTEMS

by Ahmad Atriss

  Abstract-This disclosure describes a new design approach being used in order to improve the pll acquisition (lock-in) time. A new circuit is added in order to initialize the loop filter node at a voltage level close to the center between VDD and VSS so that the lock-in (acquisition) time of the phase-locked loop system will have an improvement (reduction) of at least 10 times over present state of the art of HCMOS technology. The loop filter is a part of a high fre- quency phase locked loop system which is used as a part of a high performance data communication chip.

CIRCUITS' REALIZATION AND PERFORMANCE

  Vcntrlb.det circuit is shown in fig. 2. The purpose of this circuit is to force the loop filter node (Vcntrlb) to operate at a voltage value close to 2.5~ and the VCO frequency (Fosc) close to N times the reference frequency. At the beginning of the operation of the pll system, The Vcntrlb node voltage could start at VDD, or VSS, or anywhere behveen VDD and VSS. The Vcntrlb.det circuit will discharge or charge the Vcntrlb node to anywhere between 2.1~ to 2.6~ depending on process and temperature conditions. Setting the Vcntrlb node at the operating point will take anywhere behveen .2usec to 1.2usec depending again on process and temperature conditions.

  In fig. 2 transistors MN9 and MN8 have large W/L ratio so that they will charge or discharge the Vcntrlb node quickly. Transistors MN5 and MN6 act as comparator circuit. Transistors MNl-MN3 and MPl-MP3 form a Schmitt trigger inverter which responds nicely to very slow rising or falling signals. At the beginning of the operation of the chip, a signal (RESET-PULSE) of narrow pulse is generated. The MPD transistor will be activated. The RESET- FORCE signal will be active high. If Vcntrlb is start- ing at 5v then the output of the Schmitt trigger inverter (which is low) will be compared to the output of MN4

(which is high)...