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A SINGLE-POLY C-BiCMOS PROCESS WITH ADVANCED ITLDD CMOS AND SELF-ALIGNED VERTICAL NPN, PNP DEVICES

IP.com Disclosure Number: IPCOM000006237D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-17
Document File: 2 page(s) / 84K

Publishing Venue

Motorola

Related People

Yee-Chaung See: AUTHOR

Abstract

BiCMOS process has received much attention for high-speed applications. However, scaling of the con- ventional BiCMOS processes and devices to sub-pm has raised some issues. Reduction of supply voltage is necessary for conventional sub-pm MOSFETs due to 'reliability concerns (especially HCI). This reduction causes delay and reduced output voltage in the BiC- MOS gates due to the fixed Vbe drops in NPN. To minimize the impact of voltage reduction, CBiCMOS processes having vertical PNP devices may be used. These processes usually are very complicated and high cost.

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MOTOROLA INC. Technical Developments Volume 13 July 1991

   A SINGLE-POLY C-BiCMOS PROCESS WITH ADVANCED ITLDD CMOS AND SELF-ALIGNED VERTICAL NPN, PNP DEVICES by Yee-Chaung See

INTRODUCTION

  BiCMOS process has received much attention for high-speed applications. However, scaling of the con- ventional BiCMOS processes and devices to sub-pm has raised some issues. Reduction of supply voltage is necessary for conventional sub-pm MOSFETs due to 'reliability concerns (especially HCI). This reduction causes delay and reduced output voltage in the BiC- MOS gates due to the fixed Vbe drops in NPN. To minimize the impact of voltage reduction, CBiCMOS processes having vertical PNP devices may be used. These processes usually are very complicated and high cost.

  ITLDD CMOS with selectively deposited poly gates with improvement of HCI to CMOS has been demonstrated(l). A process which integrates this ITLDD MOSFETs and complementary vertical bipo- lar devices is proposed.

PROCESS DESCRIPTION

implants for NMOS and PMOS are masked and implanted. (Fig. 1) For simplicity, only NMOS and NPN are shown. Structures for PMOS and PNP devices are similar and complementary to NMOS and NPN, respectively.

* Poly-B (-2750A) is selectively deposited on exposed mottoSi areas and subsequently doped.

* LTO is stripped. Gate and emitter electrodes are formed. (Fig. 2)

* LDD and Link regions are formed by masked implants.

* Spacer dielectric is deposited; RIE etches spacer and polyA. This forms the...