Browse Prior Art Database

IMPROVED DATA TRANSFER SYNCHRONIZATION MECHANISM

IP.com Disclosure Number: IPCOM000006241D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-18
Document File: 3 page(s) / 129K

Publishing Venue

Motorola

Related People

Mark G. Spiotta: AUTHOR

Abstract

When transferring data between two asynchronous devices via an intermediate mailbox register, some fortn of synchronization mechanism is required to pre- vent the mailbox from being updated at the same time that it is being read. The most prevalent hardware synchronization mechanism is double-buffering, which allows the first buffer to be updated while the second buffer is simultaneously accessed. This tech- nique works well and is efficient when a small number of mailboxes are involved. However, because a dou- ble-buffered mailbox requires over twice the amount of circuitry as an unprotected mailbox, the cost of double buffering can be prohibitive when a large array of mailboxes needs to be protected.

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MOTOROLA INC. Technical Developments Volume 13 July 1991

IMPROVED DATA TRANSFER SYNCHRONIZATION MECHANISM

by Mark G. Spiotta

  When transferring data between two asynchronous devices via an intermediate mailbox register, some fortn of synchronization mechanism is required to pre- vent the mailbox from being updated at the same time that it is being read. The most prevalent hardware synchronization mechanism is double-buffering, which allows the first buffer to be updated while the second buffer is simultaneously accessed. This tech- nique works well and is efficient when a small number of mailboxes are involved. However, because a dou- ble-buffered mailbox requires over twice the amount of circuitry as an unprotected mailbox, the cost of double buffering can be prohibitive when a large array of mailboxes needs to be protected.

  This improved synchronization mechanism is ideal for protecting a large array of mailboxes. To synchronize N mailboxes, this approach only requires about (N + 1) equivalent mailboxes, while conven- tional double buffering requires over (2N) equivalent mailboxes.

  The synchronizing mechanism consists of several major components: 1) An interface to the transmitting device, 2) A transmit data latch, 3) multiple data Mail- boxes, 4) multiple Mailbox Write Access Controllers, and 5) An interface to the receiving device. A block diagram is shown in figure 1.

  The Transmitting Device Interface provides the information destined for the Mailbox as well as a strobe signal indicating when the data is valid and should be latched into the Mailbox. The Transmit Data Latch block passes the mailbox-bound transmit- ter data to the mailbox; However, under certain condi- tions, it will latch in the transmit data to maintain it even when the transmitting device is no longer send- ing it. The data Mailboxes are the physical communi- cation device-typically a set of registers. Key to this improved mechanism are the Mailbox Write Access Controllers, as shown in Figure 2. These blocks syn-

chronize the Mailbox updates with the Mailbox read cycles. Finally, the Receiving Device Interface pro- vides a data path from the Mailbox to the receiving device, along with a signal indicating when a data transfer is requested.

  Two modes of operation are possible: Non-over- lapping and Overlapping. Normally, the transmitting device's mailbox write cycle does not overlap with the receiving devices mailbox read cycle. In this non- overlapping mode of operation, the synchronizing mechanism is transparent. The Transmit Data Latch is operating in the 'transparent' mode, and both th...