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IMPROVED GExSI1-x w MOSFET WITH Ge MONOLAYER INSERTION

IP.com Disclosure Number: IPCOM000006243D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-18
Document File: 3 page(s) / 156K

Publishing Venue

Motorola

Related People

X. Theodore Zhu: AUTHOR [+2]

Abstract

There is currently considerable interest in MOS- gated Ge,Si,., heterostructures [l-4] to improve pMOS device performance. By burying a layer of narrow gap Ge,Si,., under the gate of a pMOS transistor, one creates a potential well in the valence band to confine holes in the high-performance Ge,Si,., layer. Unfortunately, the valence band-edge offset AE, at the Ge,Si,JSi interface is not large enough to adequately confine the holes. For example, for the case of com- monly used Ge fraction of x=0.2 the offset is a mere AE,=O.l5eV.

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MOTOROLA INC. Technical Developments Volume 13 July 1991

IMPROVED GE,SI,., MOSFET WITH Ge MONOLAYER INSERTION

by X. Theodore Zhu and Herb Goronkin

  There is currently considerable interest in MOS- gated Ge,Si,., heterostructures [l-4] to improve pMOS device performance. By burying a layer of narrow gap Ge,Si,., under the gate of a pMOS transistor, one creates a potential well in the valence band to confine holes in the high-performance Ge,Si,., layer. Unfortunately, the valence band-edge offset AE, at the Ge,Si,JSi interface is not large enough to adequately confine the holes. For example, for the case of com- monly used Ge fraction of x=0.2 the offset is a mere AE,=O.l5eV.

  Shown in Fig. 1 arc the simulated hole concentra- tions in the Ge,,,Si,,, well and at the Si-SiO, interface for a structure comprised of a gate oxide of lOO& a Si spacer layer of 20,& and a coherently strained Ge,.,Si,, epitaxial layer of lOOA. As the negative bias is increased from the threshold voltage the holes are induced predominantly to the well. However, due to the small value of the well depth, A& = O.lSeV, the added holes can no longer be confined inside the well as the negative bias is further increased. The number of holes diverted into the Si spacer layer increases rather quickly and surpasses the number of holes in the intended well at V,=3.5V.

increase the effective hole-confinement potential. The technique of monolayer insertion has recently been developed [.5,6] for III-V compound semiconductors to artificially maneuver the wavefunctions and energy levers of a host crystal in a controlled manner. As shown in Fig. 2, the effect of inserting a few monolay- ers of Ge is to embed a mini-well into the host Ge,Si,., well. We have plotted in Fig. 2 the valence band dia- gram of such a structure consisting of a loo.& gate oxide, a 20.& Si spacer, and a lOOA Ge,,,Si,, host well. Two monolayers of Ge are inserted 1OA away from the Ge,,Si,,$Si interface to achieve a maximum reduc- tion in ground state energy, since at that position the probability density of the holes is maximum in the lowest subband of the host Ge,,,Si,,, well.

  Assuming that the two Ge monolayers form a square quantum well potential with a width of 2.715A and a depth of 0.59eV in the host Ge,,,Si,,, well, we have calculated energy levels, wavefunctions, and hole concentrations of the system as given in Fig. 2 by solving self-consistently the Schrodinger and Poisson equations. The two dashed lines in Fig. 2 correspond to the calculated first two energy subbands of the sys- tem. The ground state is found to be affected most by the insertion of the Ge monolayers. Without the inser- tion, the ground state energy is 24.2meV above the Fermi energy, i.e., E,,-E,=24.2meV, and the probabil- ity density has a broad peak near the Ge,,,Si,$Si inter- face resulting the above mentioned diversion of the holes into the spacer layer. With the insertion of the two monolayers of Ge, the ground state ener...