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DUAL CLOCK FLIP FLOP Resolving Skew Between Commonly Generated Clocks

IP.com Disclosure Number: IPCOM000006244D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-18
Document File: 3 page(s) / 133K

Publishing Venue

Motorola

Related People

Richard A. Erhart: AUTHOR

Abstract

Skew problems between clocks continues to be a source of design problems in modem circuit design. Circuits which must communicate with each other but use clock sources emanating from different locations or sources have to resolve the skew problems between these clocks to communicate properly. This can be an intensive simulation problem in both board level or IC level design. The parasitics due to the physical layout must be estimated for proper simulation. This paper discusses a new design for a Flip Flop that will resolve these problems without intensive simulation by the designer. The cost is minimal because the Flip Flop can be designed as a custom element and then used in a "Cell Design" approach.

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MOTOROLA INC. Technical Developments Volume 13 July 1991

DUAL CLOCK FLIP FLOP Resolving Skew Between Commonly Generated Clocks

by Richard A. Erhart

ABSTRACT

  Skew problems between clocks continues to be a source of design problems in modem circuit design. Circuits which must communicate with each other but use clock sources emanating from different locations or sources have to resolve the skew problems between these clocks to communicate properly. This can be an intensive simulation problem in both board level or IC level design. The parasitics due to the physical layout must be estimated for proper simulation. This paper discusses a new design for a Flip Flop that will resolve these problems without intensive simulation by the designer. The cost is minimal because the Flip Flop can be designed as a custom element and then used in a "Cell Design" approach.

INTRODUCTION

  When transferring data between two points using synchronous sequential logic elements, the problem of clock delay between the source and the destination must be resolved. If the clocks are physically identi- cal then there is no delay. If the clocks are generated separately (may even be multiples of one another) then there is a delay (skew) between the active transi-

tions of the two clocks. If this delay approaches the delay time of the data being passed between the two points then a race condition may exist between the data and the clock. The race condition is present when a change in data appears at the destination before the active transition of the clock at the destination flip flop. The new flip flop design presented here solves the skew problem and may be employed at either the source or the destination. It will prevent race condi- tions between two synchronous but phase skewed clocks.

  The environment for this flip flop would be any circuit design having data transfer between two clock regimes which have an integer multiple synchronous relationship and an unknown phase relationship.

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OPERATION

  The operation of this design is best described by referring to figures 1, 2, and 3. Flgure 1A illustrates a configuration used in prior art. For the purposes of the following discussion assume that the only delays pre- sent in any of the circuitry are the ones shown, in other words, the internal delays in the circuit elements are included in the delays shown. A transition at time t on node n will be indicated by t,, therefore the delay between nodes 1 and 3 will be t,-t,.

  In figure lA, data is being transmitted from clock regime A to clock regime B. The two clocks are phys- ically separate nodes but are derived from a similar source, a crystal in this example. The two clocks may be integer multiples of one another. In addition the two clocks will have a different delay from the crystal transitions (at time tL) to the transitions at points labeled 2 and 3 (at times ti and tl). Whenever the tran- sitions on node 2 lead the transitions on node 3 (t,...