Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

DYNAMIC CLOCK CONTROL FOR MICROPROCESSOR SYSTEM ENERGY MANAGEMENT

IP.com Disclosure Number: IPCOM000006294D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-20
Document File: 2 page(s) / 116K

Publishing Venue

Motorola

Related People

Charles P. Schultz: AUTHOR

Abstract

When a microprocessor-based system is controlled by Operating System software that has task prioritization capabilities, a lower level task is executed when higher level tasks are idle. For energy conservation purposes, the lowest level task should put the processor into some idle, low-power mode. When the lowest level task is reached (all other tasks are idle) a large portion of the operating time of the system, this indicates that the clock rate of the microprocessor can be slowed down to con- serve energy without sacrificing system performance. When the system is operating at its low speed and the lowest level task is only reached a very small portion of the time (or possibly never), this indicates that the pro- cessor may not be performing the low-level tasks often enough to insure proper system performance, so the clock should be sped up. There may also be identifiable "critical" operations which require the processor to oper- ate at the highest possible speed to ensure performance compliance; clock control should be disabled for the duration of the "critical" operation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 2

@ MOTOROLA INC.

Technical Developments Volume 14 December 1991

DYNAMIC CLOCK CONTROL FOR MICROPROCESSOR SYSTEM ENERGY MANAGEMENT

by Charles I? Schultz

   When a microprocessor-based system is controlled by Operating System software that has task prioritization capabilities, a lower level task is executed when higher level tasks are idle. For energy conservation purposes, the lowest level task should put the processor into some idle, low-power mode. When the lowest level task is reached (all other tasks are idle) a large portion of the operating time of the system, this indicates that the clock rate of the microprocessor can be slowed down to con- serve energy without sacrificing system performance. When the system is operating at its low speed and the lowest level task is only reached a very small portion of the time (or possibly never), this indicates that the pro- cessor may not be performing the low-level tasks often enough to insure proper system performance, so the clock should be sped up. There may also be identifiable "critical" operations which require the processor to oper- ate at the highest possible speed to ensure performance compliance; clock control should be disabled for the duration of the "critical" operation.

  In order to establish whether the processor is spend- ing too much or too little time in the lowest level (WAIT) task, two counters should be established. One counter is active when the processor is in the WAIT task, and one is active when the processor is not in the WAIT task. Many modern microcontrollers provide a free-running counter and output compare registers, Also, real-time clock devices exist that readily interface to microprocessor systems.

  To implement operation using the free-running coun- ter (FRC) and output compare register system, a "window" of observation is established by a number that is added to the present contents of the FRC. When the FRC reaches this new value, the ratio of processing to non-processing (WAIT) time will be compared to determine clock speed effectiveness. The present value of the FRC is also noted for calculation of times spent in processing and non-processing states. Once the lowest

level task is reached, the initial value of the FRC is subtracted from its new value, and this number is accu- mulated in a memory location which acts as a Processing Task Accumulator (PTA). This can be expressed mathematically as:

PTA = PTA + (new FRC - old FRC), old FRC = new FRC

  When processing resumes, that is, the WAIT state is exited, the value of the FRC when the WAIT state was entered is subtracted from the current value of the FRC, and this number is accumulated in a memory loca- tion act...