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SUB-LITHO GATE LENGTH TECHNIQUE FOR DEEP SUBĀµ CMOS/BICMOS APPLICATIONS

IP.com Disclosure Number: IPCOM000006309D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-24
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Bor-Yuan Hwang: AUTHOR [+3]

Abstract

This process technique described here can achieve a short gate poly length with precise control down to sub- litho geometry. Standard process steps are used to achieve this structure without applying processes beyond the pres- ent technology capability. This sub-litho gate poly length definition alIows tier improvement in MOS device per- formance by reducing Leff without sacrificing the excessive overlapping capacitance between gate to source and draii (Cgd and Cgs).

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MOTOROLA INC. Technical Developments Volume 14 December 1991

SUB-LITHO GATE LENGTH TECHNIQUE FOR DEEP SUBp CMOS/BICMOS APPLICATIONS

by Bor-Yuan Hwang, Margaret Huang and hfan Rahim

1. INTRODUCTION

  This process technique described here can achieve a short gate poly length with precise control down to sub- litho geometry. Standard process steps are used to achieve this structure without applying processes beyond the pres- ent technology capability. This sub-litho gate poly length definition alIows tier improvement in MOS device per- formance by reducing Leff without sacrificing the excessive overlapping capacitance between gate to source and draii (Cgd and Cgs).

2. PRIOR ARTS

  To achieve a shorter Leff and/or sub-litho gate length for either performance improvement or deep sub-p device study is desirable. Various techniques either published in the literature or commonly used in industry are sum- marized in the following.

a. Lateral diffusion This method can reduce Leff, it however increases the overlap capacitance and thus trading perfor- mance off.

b. Over exposure at gate photo processing This method suffers from the control problem.

c. Over etch hard mask This method also suffers from the control problem in etch the hard mask laterally underneath the photo resists (Figure 1).

d. SST elevated electro approach (~760, IEDM 1988, NTT)

This method has the disadvantages in constructing LDD, GOI, and excessive overlap CgdKgs capacitance.

e. MOSIAC SA (Bicmos process, FAST by Peter Zdebel, Motorola)

This method has basically the same stmcture as the NTI Bicmos SST. Therefore the same limitations applied.

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