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ADDING EXTRA ADDRESS REGISTERS IN A CORE ENVIRONMENT

IP.com Disclosure Number: IPCOM000006312D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-24
Document File: 3 page(s) / 149K

Publishing Venue

Motorola

Related People

Joseph Gergen: AUTHOR [+2]

Abstract

A new feature has been added which allows a user to add up to four additional address register sets (Rn/Mn/Nn) outside of the DSP5616 core micro- processor. Depending on the needs of the user's appli- cation outside of the core, the user can provide extra address register(s) as well as a peripheral address gener- ation unit (AGU) for performing address calculations and updates. The user only implements the capability needed by the application.

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MOTOROLA INC. Technical Developments Volume 14 December 1991

ADDING EXTRA ADDRESS REGISTERS IN A CORE ENVIRONMENT

by Joseph Gergen and Tan Nhat Dao

1. INTRODUCTION

  A new feature has been added which allows a user to add up to four additional address register sets (Rn/Mn/Nn) outside of the DSP5616 core micro- processor. Depending on the needs of the user's appli- cation outside of the core, the user can provide extra address register(s) as well as a peripheral address gener- ation unit (AGU) for performing address calculations and updates. The user only implements the capability needed by the application.

  This feature is useful for providing extra address reg- ister set(s) for interrupt handler routines, so that alI four address register sets on the core are available for use by the main program. The feature is usually act&d when an inter- rupt is received and an extra register set is required by the titerrupt handler. It is then disabled when returning back to the main program. The feature is not, however, limited to a single interrupt handler and can be used in the main program or in more than one interrupt handler if desired.

2. HARDWARE PROVIDED ON THE DSP5616 CORE

   On the DSP core, a new OMR bit, PE, has been added, as well as a new SR bit, AD. Additional circuitry has been added for appropriately disabling the DSP5616 core's address generation unit and a peripheral AGU control bus now comes out of the core to allow the peripheral AGU to recognize DSP5616 addressing needs.

3. HARDWARE PROVIDED BY

THE USER OUTSIDE THE CORE

  The user must provide all of the additional address registers required. Each register is read and written by the core as a memory mapped peripheral register, and these registers are used for generating and updating addresses when the Peripheral AGU feature is appro- priately enabled. In addition, the user must also provide an ALU for all peripheral address register updates, and cimihy for generating read and 'write signals for accessing the additional memory mapped registers.

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  The peripheral ALU provided by the user is typi- cally much simpler than the module arithmetic unit found on the DSP5616 core. For example, many users do not need the reverse carry capability and would not imple- ment it here. Likewise, a simple comparator and a reg- ister containing a buffer's base address could replace the core's module capability for applications which incre- ment a pointer. Also, if the size of the user's buffer is a power of two and located on a power of two boundary, the module operation could be done with an ANDing operation. In some cases, this ALU may be as simple as an n-bit adder.

  The feature is enabled as shown in Fire 1 by setting the PE bit in the OMR. Once this bit is set, the peripheral AGU is used (and the core's AGU disabled) during alI fast interrupt routines. It will drive the xabl address bus instead of the core, and using signals 6om the core, will update the peripheral's add...