Browse Prior Art Database

CMOS READ ONLY MEMORY SENSE AMP

IP.com Disclosure Number: IPCOM000006313D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-24
Document File: 2 page(s) / 107K

Publishing Venue

Motorola

Related People

Steven E. Cozart: AUTHOR [+2]

Abstract

This has advantages over differential sensing tech- niques depicted in Figure 2 by eliminating the circuitry and power those circuits consume both in the reference leg of the diffential sense amp and the reference genera- tion circuits used to bias the reference leg (MNS, MP5).

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MOTOROLA INC. Technical Developments Volume 14 December 1991

CMOS READ ONLY MEMORY SENSE AMP

by Steven E. Cozart and Mark E. Burchfield

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  This has advantages over differential sensing tech- niques depicted in Figure 2 by eliminating the circuitry and power those circuits consume both in the reference leg of the diffential sense amp and the reference genera- tion circuits used to bias the reference leg (MNS, MP5).

  The cascode stage of,, the single ended sense amp (MNll, MPll, MN12, MP12) in Figure 1 provides a cur- rent source to the bitlimes of the memory core. The plug transistor sinks this current, and holds the voltage on node COL to approximately a Vtn (0.8 volts). This prevents MN13 from conducting.which is not the case of MN13 of the differential sense amp of Figure 2. If there is no such plug, the current charges the capacitance of the column. The feedback of MN11 and MNl2 limits this charging and the column voltage levels off about mid-supply (2.5 volts) by dropping the voltage through one triode connected P Channel (MPll) a Vtp and one cascode connected N Channel (MN12) a Vtn. Therefore the voltage, on only one of the heavily loaded bit lines due to the column decode, (BLl through BLn) is limited to swing Tom VSS to approx- imately 2.5 volts for no array transistor conducting current. The power consumed by, discharging of the bit line is shown by the equation Power = Capacitance times Volt- age times Voltage times Frequency or C*V*V*E If the voltage swing is reduced, then the power is reduced by the square of the voltage. The voltage potential at node N2 tracks along with the node COL but is shifted upward due to the drop across MN12. The 'triode connected' MP12 clamps the upper limit of N2 to Vdd-Vtp (4.2 volts). When there is a plug, the potential of N2 is lowered to near mid-supply. By placing an N-channel (MN13) gated by COL and a P-channel (MP13) gated by N2, I have formed a very sensitive inverter. Since COL drops to approximately Vtn when there is a plug, and N2 climbs to Vdd-Vtp when there is no plug, no steady state current flows in either MP13 or MN13, but its output (node SA) still swings to full CMOS levels. The bitlines ofthe memory core are precharged low. Since the sense amp sources current to the array through the column transfer devices, only selected bitlines will be charged. Likewise, because the array is...