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STRUCTURE FOR REDUCED SOURCE AND DRAIN AREA BY SELECTIVE SILICON

IP.com Disclosure Number: IPCOM000006321D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-25
Document File: 3 page(s) / 137K

Publishing Venue

Motorola

Related People

Jon Fitch: AUTHOR [+4]

Abstract

The spacing between adjacent gate lines in submicron technology is limited by the minimum isolation spacing and by the minimum source and drain window size necessary to form a contact. If one could reduce the source and drain window size then, for the same isola- tion spacing, one could realize (1) an improvement in device packing density and (2) a reduction in S/D junction capacitance.

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MOTOROLA INC. Technical Developments Volume 14 December 1991

STRUCTURE FOR REDUCED SOURCE AND DRAIN AREA BY SELECTIVE SILICON

by Jon Fitch, Carlos Mazurk, Dean Denning, and Jim Pfiester

DEFINITION OF PROBLEM

  The spacing between adjacent gate lines in submicron technology is limited by the minimum isolation spacing and by the minimum source and drain window size necessary to form a contact. If one could reduce the source and drain window size then, for the same isola- tion spacing, one could realize (1) an improvement in device packing density and (2) a reduction in S/D junction capacitance.

PRIOR ART

  The most common scheme for reducing source and drain area is to pattern smaller source and drain win- dows and use selective epi to overgrow the isolation and increase the contact area this way. This approach has two problems: (1) the source and drain window widths are limited by the registration accuracy of the photoli- thography (i.e. gate poly to active registration accuracy), and (2) under normal circumstances it is very difficult to achieve epi lateral overgrowth ratios greater than 0.6 to 1.

INVENTION AND PROBLEM SOLUTION

A substantial improvement in packing density and a reduction in S/D junction capacitance can be realized by

the reduced source and drain area structure we propose:

(1) Form a MOSFET gate structure with a thick LTO layer on top of the gate poly (-2.000& and a thin (SOO-1,OOOA) nitride cap on top cf the LTO (see Figure 1). Etch thin (- l,OOOA) TEOS sidewall spacers.

(2) Deposit a thick layer of nitride (-2,000$ and etch nitride sidewall spacers along the gate on top ofthe TEOS spacers (see Figure 2).

(3) Perform a sfcondary field oxidation step (2,000-4,OOOA) to oxidize the exposed source and drain areas not covered by the nitride spacers (see Figure 3).

(4) Use an isotropic etch which is selective to oxide and to silicon to remove the nitride sidewall spacers and capping layer (see Figure 4).

(5) Eleva~edomurce and drains (see Figure 5): grow -3,500A of SEG to form elevated source and drain regions. Form poly spacers along the SEG and do a second selective silicon step to grow the source and drain contacts out over the iso- lation, using the poly spacers as a seed for lat- eral overgrowth. Note that a photo and etch

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MOTOROLA INC. Technical Developments Volume 14 December 1991

step is necessary aIter poly spacer formation to remove the spacers from gate line edges out- side of the active area.

Conventional source and drain contmction (see Figure 6): form poly spacers and do a photo and etch step to remove spacers from gate line...