Browse Prior Art Database

HIGH SELECTIVITY CONTACT ETCH FOR BiCMOS AND CMOS

IP.com Disclosure Number: IPCOM000006323D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-25
Document File: 2 page(s) / 87K

Publishing Venue

Motorola

Related People

Bob Reuss: AUTHOR [+2]

Abstract

As circuit features have been reduced to the l/./m range, the difficulty of opening contacts has increased significantly, While there are several important aspects to a successful contact etch, the ability to completely clear. oxide (or other dielectric) from the window without removal of the underlying substrate is perhaps the most critical. The margin between overetch (which can create shorted or leaky junctions) and underetch (which results in high resistance or opens) is narrowed because VLSI devices require shallow junctions while advanced multilayer metal systems require planarization of the thick (0.5-1.0 pm) dielectric (ILDO) underneath first metal. A planarized ILDO provides process margin for metal patterning and electromigration resistance, but creates varying oxide thicknesses (tax) over the individual contacts. Since the difference in tax can be ~0.4 pm, a high selectivity etch (oxide to silicon) to minimize etching of the shallow junctions (~0.2 pm) is required.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 2

0 M

MOTOROLA INC. Technical Developments Volume 14 December 1991

HIGH SELECTIVITY CONTACT ETCH FOR BiCMOS AND CMOS

by Bob Reuss and Carl Almgren

PROBLEM

  As circuit features have been reduced to the l/./m range, the difficulty of opening contacts has increased significantly, While there are several important aspects to a successful contact etch, the ability to completely clear. oxide (or other dielectric) from the window without removal of the underlying substrate is perhaps the most critical. The margin between overetch (which can create shorted or leaky junctions) and underetch (which results in high resistance or opens) is narrowed because VLSI devices require shallow junctions while advanced multilayer metal systems require planarization of the thick (0.5-1.0 pm) dielectric (ILDO) underneath first metal. A planarized ILDO provides process margin for metal patterning and electromigration resistance, but creates varying oxide thicknesses (tax) over the individual contacts. Since the difference in tax can be ~0.4 pm, a high selectivity etch (oxide to silicon) to minimize etching of the shallow junctions (~0.2 pm) is required.

SOLUTIONS

  The obvious solution to this problem is to obtain equipment capable of increasing oxide to silicon etch selectivity ratios. However, such equipment is expen- sive and the technical challenges significantly difficult such that new tools are not necessarily a guarantee of a highly reliable process for VLSI.

  An alternative solution is to incorporate a sacrificial polysilicon layer under the ILDO. The purpose of this layer is to act as an etch stop for the z 1 C/m oxide etch. Overetch and removal of polysilicon in the contacts with the thinnest ILDO while the remaining contacts are clear- ing is of no consequence. Sufficient overetch can be pro- grammed such that all con...