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ONE-WIRE FULL-DUPLEX COMMUNICATION SCHEME

IP.com Disclosure Number: IPCOM000006333D
Original Publication Date: 1991-Dec-01
Included in the Prior Art Database: 2001-Dec-26
Document File: 2 page(s) / 92K

Publishing Venue

Motorola

Related People

Robert D. Woodhouse: AUTHOR [+2]

Abstract

Pin-count or wire quantity sometimes prove to be a limiting factor in a design. The circuitry presented here can allow for reduced count of these things by allowing pins or wires to operate in a full-duplex mode. The cir- cuitry can be built of discrete components; however, it is intended to reside on a single chip and is illustrated this way in Figure I. If the circuitry were built discretely, the savings would be a reduction of communication wires between devices, but at the cost of many extra parts. Inte- gration of the circuitry within the chip allows for both (I) reduced wire interconnects between devices with this cir- dry and (2) reduced pin count on parts with this circuitry.

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MOTOROLA INC. Technical Developments Volume 14 December 1991

ONE-WIRE FULL-DUPLEX COMMUNICATION SCHEME

by Robert D. Woodhouse and Charles C. Kim

  Pin-count or wire quantity sometimes prove to be a limiting factor in a design. The circuitry presented here can allow for reduced count of these things by allowing pins or wires to operate in a full-duplex mode. The cir- cuitry can be built of discrete components; however, it is intended to reside on a single chip and is illustrated this way in Figure I. If the circuitry were built discretely, the savings would be a reduction of communication wires between devices, but at the cost of many extra parts. Inte- gration of the circuitry within the chip allows for both (I) reduced wire interconnects between devices with this cir- dry and (2) reduced pin count on parts with this circuitry.

  For ease of explanation, let the device illustrated in Figure 1 be called device1 and the device with which it is communicating be called device2. Of course, device2 employs the new circuitry, also. Ifdeviccl wishes to trans- mit a message, it applies an appropriate binary signal to TXl. When TX1 is 'hi' (near Vcc), current flows through Ql and through a terminating resistance Rt. device1 and device2 each have a terminating resistor of a value twice Rt. The impedance of the line between the devices also should be twice Rt. This permits the claim that the current flows through a resistance Rt. This current flow through Rt produces some voltage level, Vl (VI near Vcc/2), on the communication line. If device2 holds its transmit line, TX2, 'hi' at the same time that TX1 is 'hi: then more cur- rent flows through Rt to produce some voltage level, V2 (V2 near Vcc), on the communication line.

The signal named B is the logical output of a com- parator used to determine if the communication line volt-

age is at least Vl. The signal named C i...