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METHOD FOR WET ETCH OF EMITTER CONTACT FOR CMOS BASED DOUBLE POLY BiCMOS PROCESS

IP.com Disclosure Number: IPCOM000006361D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2001-Dec-28
Document File: 2 page(s) / 86K

Publishing Venue

Motorola

Related People

Robert H. Reuss: AUTHOR [+2]

Abstract

In BiCMOS flows based on SRAM products, the NPN (Figure 1) is usually fabricated after the CMOS implants and deposition of the interpoly LTO (2-3KA) by etching an emitter contact to the active base region and then deposition of a second poly layer to serve as both emitter and load resistor! A problem with this proc- ess is that the emitter contact must be opened by RIE in order to maintain dimensional control (wet etch would give larger and variable emitter area). The RIE process requires compromises, however, because of the follow- ing trade-offs: 1. Residual oxide in the emitter window (underetch) results in catastrophic emitter resistance and poor or no emitter base junction formation.

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MOTOROLA /NC. Technical Developments Volume 15 May 1992

METHOD FOR WET ETCH OF EMITTER CONTACT FOR CMOS BASED DOUBLE POLY BiCMOS PROCESS

by Robert H. Reuss and Terry S. Hulseweh

PROBLEMS

  In BiCMOS flows based on SRAM products, the NPN (Figure 1) is usually fabricated after the CMOS implants and deposition of the interpoly LTO (2-3KA) by etching an emitter contact to the active base region and then deposition of a second poly layer to serve as both emitter and load resistor! A problem with this proc- ess is that the emitter contact must be opened by RIE in order to maintain dimensional control (wet etch would give larger and variable emitter area). The RIE process requires compromises, however, because of the follow- ing trade-offs:

1. Residual oxide in the emitter window (underetch) results in catastrophic emitter resistance and poor or no emitter base junction formation.

2. Overetch to insure removal of oxide results in lattice damage to the active area of the transistor and/or deposited residues that effect the perform- ance and reproducibility.

3. Overetch with a low selectivity process results in minimal damage, but significant etch into the active base (and lower base doping and resulting impact on device performance).

process sequence is as described below and shown in Figure 2.

1. ABer the standard CMOS portion of the flow, the tax on the silicon substrate is 200-500A.

2. Deposit 1OOOA nitride and 1OOOA poly.

3. RIE the poly stopping on the nitride using the standard emitter contact mask (selectivity > 1011).

4. Oxidize the poly to form about 2K of oxide with the nitride masking any oxidation ofthe Si.

5. Plasma or wet etch the...