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INTEGRATION OF SELF-ALIGNED POLY EMITTER NPN INTO CMOS-BASED BiCMOS

IP.com Disclosure Number: IPCOM000006362D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2001-Dec-28
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Robert H. Reuss: AUTHOR [+2]

Abstract

A standard CMOS process can be converted to a BiCMOS process by adding a few extra steps, primarily at the completion of the CMOS flow. A base region is implanted, dielectric deposited (l-3K) to isolate the CMOS devices, an opening made in the dielectric to define the emitter contact, and poly silicon deposited, doped, patterned, and annealed (Figure 1). The resulting NPN has the virtue of adding few extra steps to the baseline CMOS flow. Unfortunately, there are several significant drawbacks with this approach.

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MOTOROLA INC. Technical Developments Volume 15 May 1992

INTEGRATION OF SELF-ALIGNED POLY EMITTER NPN INTO CMOS-BASED BiCMOS

by Robert H. Reuss and Terry S. Hulseweh

PROBLEMS

   A standard CMOS process can be converted to a BiCMOS process by adding a few extra steps, primarily at the completion of the CMOS flow. A base region is implanted, dielectric deposited (l-3K) to isolate the CMOS devices, an opening made in the dielectric to define the emitter contact, and poly silicon deposited, doped, patterned, and annealed (Figure 1). The resulting NPN has the virtue of adding few extra steps to the baseline CMOS flow. Unfortunately, there are several significant drawbacks with this approach.

1. The portion of the extrinsic base between the P+ contact implant and the intrinsic base (known as link base) is also the active base. To achieve accept- able characteristics such as gain (beta), breakdown, and frequency response, the active (and therefore link) base region must be relatively lightly doped. This results in higher base resistance which degrades both gate delay and noise characteris- tics ofthe device.

2. A second problem is that opening of the emitter contact requires RIE to remove the deposited oxide over the active transistor region. The use of RIE presents significant control and reproduci- bility problems which can be avoided if a wet etch is substituted.

1. Standard CMOS (BiCMOS) flow thru deposi- tion of interpoly LTO (omit only active base implant). Note overlap of P+ base contact implant in Figure 2a.

2. Use masked wet oxide etch to remove oxide t?om active area of NPN.

3. Grow thin oxide (200-5OOA) over the NPN and deposit poly (500-lOOA) and nitride (2000A).

4. Masked nitride etch to define emitter dimensions.

5. Maskless implant of link base to connect P+ base contact with edge of emitter (dose lE14-lE15) with sufficient energy to go through thin poly and oxide but not thru nitride (th...