Browse Prior Art Database

SYNCHRONIZATION VALIDATION APPARATUS FOR ENCRYPTED DATA

IP.com Disclosure Number: IPCOM000006366D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2001-Dec-28
Document File: 2 page(s) / 138K

Publishing Venue

Motorola

Related People

Michelle Bray: AUTHOR [+2]

Abstract

This invention solves the problem of achieving syn- chronization while using encryption devices whose syn- chronization requirements are inherently unknown. Unless sync is achieved, data will not be decryptable. In the Advanced Securent (ASN) System, such synchroniz- ation failures can lead to corrupted data being stored in a database and a high error rate in an over-the-air-rekeying (OTAR) message to a subscriber unit.

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@ MOTOROLA INC.

Technical Developments Vplume 15 May 1992

SYNCHRONIZATION VALIDATION APPAR$"S

FOR ENCRYPTED DATA ~

by Michelle Bray and David lngham ~

1:

INTRODUCTION

  This invention solves the problem of achieving syn- chronization while using encryption devices whose syn- chronization requirements are inherently unknown. Unless sync is achieved, data will not be decryptable. In the Advanced Securent (ASN) System, such synchroniz- ation failures can lead to corrupted data being stored in a database and a high error rate in an over-the-air-rekeying (OTAR) message to a subscriber unit.

  The Advanced Securenet system uses a 256 bit sync sequence. Without this invention, synchronization, even over an error-free channel, could not be reliably achieved using DVI-XL, and DVP-XL encryption algorithms. The chances of these systems gaining sync using a 256 bit sync sequence is approximately 96%. As more bits are devoted to synchronization, the probability of synchronization increases; but without this invention, synchronization cannot be absolutely guaranteed.

CIPHER FEEDBACK ENCRYPTION AND DECRYPTtON IN THE DVI-XL AND DVP-XL ENVIRONMENT

  This invention is applied to the Advanced Securenet Key Management Controller (KMC) when DVI-XL or DVP-XL encryptions are used, and applies equally well to any encryption system in which a futed, error-free sync sequence cannot guarantee synchronization. The invention is implemented in the KMc's encryption proc- essor, which handles the KMC's encryption and decryption processes. The data processed by the KMC is key data, which is stored encrypted on the KMC host hard disk and is also sent over-the-air for the purpose of remotely rekeying radio subscriber units.

  A cipher feedback encryption/decryption system is shown in Figure 1. To encrypt, the plain text in (F'D) sequence of 256 sync bits followed by 160 data bits is input into the encryption device. The output of the device's key generator (KG), the key stream, is XORed with the PfI to form the cipher text out (CTO) which is

fed back into the encryption\device's N-bit shii register. This signal is also bansmittd~~o the receiving device, where it is input as cipher text in (C$. In the receiver, the CT0 is fed directly into the shit? register. Assuming the transmitting and receiving devices are using the same key, the plain text out (PfO) of the receiving device will match the plain text in (PTI) of the transmitting device after N consecutive error- Ike Cll bits till the receiving shift register As long as N, the shitl register length, is less than 256 bits, such a system is guaranteed to provide sync assuming an error-6ee channel.

  Figure 2 shows a system in which synchronization is not guaranteed. In this system, data from the receiver's shii register is not input into the KG unless it contains a specific sequence of bits. The particular bit sequence is a function of the key and is unavailable outside the encryption and decryption devices. Therefore, althou...