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Method for a complimentary device CMOS circuit design

IP.com Disclosure Number: IPCOM000006377D
Publication Date: 2001-Dec-28
Document File: 10 page(s) / 77K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a complimentary device CMOS (CD-CMOS) circuit design. Benefits include improved power consumption, improved gate support, and reduced capacitance, gate area and gate leakage

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Method for a complimentary device CMOS circuit design

Disclosed is a method for a complimentary device CMOS (CD-CMOS) circuit design. Benefits include improved power consumption, improved gate support, and reduced capacitance, gate area and gate leakage.

Background

              Conventional process technologies support dual-threshold (Vt) devices so that speed critical circuit paths can meet timing by using the faster low-Vt transistors. However, the low-Vt devices have subthreshold leakage that is approximately 10 times greater than high Vt transistors. Therefore, the power consumption of the design goes up dramatically with the percentage of low Vt transistors used. Under conventional design methodology, the team tries to meet the timing goals of the project using high-Vt devices. Some high-Vt devices are replaced by low-Vt devices in critical paths that cannot meet timing requirements and cannot be architecturally modified (for various reasons from schedule to performance impact).

              Several automated tools perform this replacement. One software tool attempts to converge timing by considering high-Vt and low-Vt library cells simultaneously. One critical difficulty is that these tools fundamentally attempt to meet timing goals as the first priority. Performing power trade‐offs is very difficult, if supported at all. In all the methodologies (either post processing the netlist or creating special low-Vt library cells), high-Vt NMOS devices are replaced with low-Vt NMOS devices, and high-Vt PMOS devices are replaced with low-Vt PMOS devices, either by the software tools or manually in custom circuit designs.

Description

              At a very high level, the disclosed method (CD‐CMOS) seeks to leverage dual-Vt-process technologies by realizing that active and leakage power savings area reduction (or at least break even) and in exchange for a small delay penalty.

              Another distinguishing feature of this method is that it provides for single stage non‐inverting gate implementations yet is still a static-circuit style. Conventional static CMOS circuit designs only support inverting gate cells. Some differential circuit styles (such as DCVS) require each input and its compliment to be available. These styles generate the output and output complement. Dynamic styles (such as domino) require an extra inverting stage between them so as to appear to generate non‐inverting gates. This approach is well documented. This circuit style consumes much more power than static CMOS circuits even though, in some cases, they may provide a speed improvement. A few circuits, however, use differential circuits that make sense because the input and the complement of the input are required and are also required to be generated.

              If a non‐inverting logic function is required while using static CMOS gates, two inverting gates must be used together to achieve the non‐inverting function. For example, conventional CMOS uses a NAND gate (see Figure 1) followed by an INVERTER gate to realize an AND gate (...