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Method to reconfigure electrodes/pads on an existing capacitor to provide low inductance

IP.com Disclosure Number: IPCOM000006386D
Publication Date: 2001-Dec-28
Document File: 3 page(s) / 1K

Publishing Venue

The IP.com Prior Art Database

Abstract

The disclosed method modifies the metal pattern on commercial chip capacitors or similar objects by depositing and/or ablating metals.

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Method to reconfigure electrodes/pads on an existing capacitor to provide low inductance

Background

              The conventional electrode pad layout in chip capacitors is not conducive to low inductance connections. The available parts either have too few terminals (the most common and cheapest capacitors have 2-terminals) or too little electrode surface area available on the bonding surface. Conventional manufacturers work around the inherent problems by creative layout and other means. The “striped cap” was one attempt that provided more surface area.

              Capacitor electrode material is derived from glass frit/metal paste so that resistivity is often too high and is difficult to control.         No easily available conventional means exists for controlling the ESR (parasitic resistance) of a multiplayer ceramic capacitor (MLCC). Any materials used prior to part firing must be co-fired with the ceramic and metal part. Not only can this involve temperatures of 1000º C or higher, but careful control of the firing atmosphere and part chemistry are often required. Materials selection for resistive contacts or layers is therefore greatly limited, unless a way is found to apply materials to the part after firing.

General description

              The disclosed method modifies the metal pattern on commercial chip capacitors or similar objects by depositing and/or ablating metals.

              Selective deposition is used to reroute the existing electrode pads of a chip capacitor. The pairs of electrodes with the same polarity are shorted together with a metal layer, reconfiguring them into a lower inductance design. Compared to the original pads, many vias can be connected to this enlarged electrode, significantly decreasing the loop inductance.

Advantages  

              The disclosed method provides several advantages over the conventional solution, including:

·        Lower inductance and increased resistance

·        No masks are required                                 

·        No Litho step is required                                       

·        No patterning or etching of metal films                                         

·        Adaptable to odd size substrate, capacitors        

·        Amenable to customization                                  

·        Low cost solution as compared to array capacitors

·        Ability to deposit alternative electrode materials, for example gold to allow for wire-bonding

·        ~3.6-fold increase in top-surface pad area

·        Potential ability to deposit resistive materials to crea...