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Method for Using a 16-Bit Signed Multiplier for 32 x 16 Multiplication

IP.com Disclosure Number: IPCOM000006387D
Publication Date: 2001-Dec-28
Document File: 2 page(s) / 1K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for implementing 16 x 32-bit multiplication. The disclosed method uses a 16-bit signal multiplier and twos complement to multiply with unsigned numbers in signed architectures.

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Method for Using a 16-Bit Signed Multiplier for 32 x 16 Multiplication

Disclosed is a method for implementing 16 x 32-bit multiplication. The disclosed method uses a 16-bit signal multiplier and two’s complement to multiply with unsigned numbers in signed architectures.

Currently, 16 x 32-bit multiplication can be implemented using two 16 x 16-bit multiplications, a shift, and a 48-bit addition as shown in Figure 1. Some architectures only support signed 16-bit multiplication. Because the number alow is unsigned, using it with signed architectures becomes a problem. One method to avoid the signed multiplier problem is to sacrifice one bit, which results in a 31 x 16-bit multiplication. The disclosed method eliminates branching and can be used in signed and unsigned architectures without sacrificing any bits.

The disclosed method exploits a property of two’s complement numbers to implement 16 x 32 bit multiplication. To calculate the two’s complement of a number, subtract the number from 2N, where N is the number of bits, in this case 16. If alow is positive, the most significant bit (MSB) is 0, and the multiplication is not affected. If it is negative (MSB=1), the multiplier uses the two’s compliment to treat alow as if the multiplier were unsigned. For example, FFFF (hex) is interpreted as 65535 by an unsigned multiplier, but as -1 by a signed multiplier. Therefore, 65535 - 65536 = -1; or 65535 = -1 + 65536. In general, alow = alows + 10000 (hex), where alows is the signed...