Browse Prior Art Database

PERIPHERAL ERROR CALCULATOR

IP.com Disclosure Number: IPCOM000006410D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-01
Document File: 2 page(s) / 87K

Publishing Venue

Motorola

Related People

Richard A. Erhart: AUTHOR [+3]

Abstract

In a pager with a microcomputer based decoder, this invention will allow a microprocessor to run at a lower bus rate when doing address correlations. During the process of address correlation, the current micro- processors require a substantial amount of ROM and/or CPU cycles to calculate the weight (number of l's) in a byte. They must either use a serial shift process and add method, or use a large look-up table method. The cycle time of correlating is particularly critical in early address shut down type battery saving. For example, the aver- age current drain increases by 1 A for every 200 micro- seconds of CPU timing used up in the correlation process using a typical paging protocol.

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MOTOROLA INC. Technical Developments ~olume15 May1992

PERIPHERAL ERROR CALCULATOFj

by Richard A. Erhart, David Hayes and Michael Delfca

  In a pager with a microcomputer based decoder, this invention will allow a microprocessor to run at a lower bus rate when doing address correlations. During the process of address correlation, the current micro- processors require a substantial amount of ROM and/or CPU cycles to calculate the weight (number of l's) in a byte. They must either use a serial shift process and add method, or use a large look-up table method. The cycle time of correlating is particularly critical in early address shut down type battery saving. For example, the aver- age current drain increases by 1 A for every 200 micro- seconds of CPU timing used up in the correlation process using a typical paging protocol.

  The invention is a relatively simple hardware block which can rapidly calculate the weight (number of l's) in a byte. Prior art designs typically employ a register for holding the word, a tree adder for summing the l's and an output register for latching the results. This inven- tion is shown in Figure 1. The word is written to a regis- ter which automatically right sh& all 1's. This guarantees that there are no Zero's between the total number of l's

in the word. The software can now interrogate this reg- ister and determine exactl; how many errors were in the word. The real benefii comes when the software only needs to determine if be number of errors exceed a predetermined number.IAn example would be the POCSAG pro...