Browse Prior Art Database

SSI ALL NPN PEAK HOLD CIRCUIT

IP.com Disclosure Number: IPCOM000006418D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-02
Document File: 2 page(s) / 85K

Publishing Venue

Motorola

Related People

Thomas J. Schuster: AUTHOR

Abstract

The implementation and operation of an SSI (small scale integration) all npn peak hold circuit is described in this article.

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MOTOROLA INC. Technical Developments Volume 15 May 1992

SSI ALL NPN PEAK HOLD ClRClJlT~,

by Thomas J. Schuster

  The implementation and operation of an SSI (small scale integration) all npn peak hold circuit is described in this article.

The peak hold design is a wideband, single chip, all npn transistor solution to a circuit function that typicalIy &or- porates both npn and pnp transistors in a hybrid pack- age. A hybrid is used because high performance pnp and npn transistors are generally not available on the same die.

  A schematic of the peak hold design is shown in figure 1, operation of the circuit is as follows: A negative going pulse is incident at VIN. The input is a negative pulse because the input driver is perceived to be a detec- tor diode and typical detectors are negative output.

  The pulse is amplified and inverted by the two dif- ferential ampliiers Ql/Q2 and Q3/Q4. Resistor R50 and the reversed biased junctions of transistors Q9-Q16 are used to increase stability. The pulse is buffered by the Q6 emitter follower to the diode Q7. The diode is forward biased and the pulse will charge hold capacitor Cl, when the VTRACK switch, Q8, is off. If the VTRACK switch is on the capacitor discharges and the peak hold functions as an amplifter. When the pulse goes away the charge is held on the capacitor by the diode and the Darlington pair, Q17 and QlS. The use of a Darlington pair decreases leakage from the charged capacitor. Hybrid designs may incorporate a FET tran- sistor for this function.

  The signal is buffered~~ to the o...