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A HIGH-SPEED 3-BIT A/D CONVERTER IMPLEMEPTED ON THE B15K TRANSISTOR ARRAY

IP.com Disclosure Number: IPCOM000006420D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-02
Document File: 4 page(s) / 174K

Publishing Venue

Motorola

Related People

Richard H. Ong: AUTHOR

Abstract

Most data detection systems use commercially avail- able 4-8 bit A/D converters which are high power and have limited bandwidths. For applications requiring less than 4 bits there are some A/D converters made from SSI components. Problems causing static sources of error with A/D converters include reference ladder resistor matching, comparator offset voltage matching, reference ladder parasitic resistance, and comparator metastable output states. Problems causing dynamic sources of error with flash converters include comparator delay mismatch, chip parasitics, aperture jitter, and front end bandwidth limitations. This invention is a single chip, high speed, fully temperature and power supply voltage compen- sated solution to the above problems.

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MOTOROLA INC. Technical Developments Vcdume 15 May 1992

A HIGH-SPEED 3-BIT A/D CONVERTER IMPLEMEPTED ON THE

B15K TRANSISTOR ARRAY ~

by Richard H. Ong I,

  Most data detection systems use commercially avail- able 4-8 bit A/D converters which are high power and have limited bandwidths. For applications requiring less than 4 bits there are some A/D converters made from SSI components. Problems causing static sources of error with A/D converters include reference ladder resistor matching, comparator offset voltage matching, reference ladder parasitic resistance, and comparator metastable output states. Problems causing dynamic sources of error with flash converters include comparator delay mismatch, chip parasitics, aperture jitter, and front end bandwidth limitations. This invention is a single chip, high speed, fully temperature and power supply voltage compen- sated solution to the above problems.

  Several modulation formats (BPSK, QPSK, or BPSK) require only three bits of resolution at extremely high sampling rates. The previous solution was to use 4 to 8 bit A/D converters and to only employ the 3 least sig- nificant output bits. The remainder of the circuitry supporting the higher bits is not necessary and wastes chip real estate and power, in addition to requiting a large package footprint. Since this invention is optimized for 3-bit operation with fewer components and reduced power requirements, improved manufacturability and reliability result. Another improvement of this architec- ture is increased bandwidth since the decoding logic is designed specifically for 3-bit operation. Current mode logic (CML) using series gating for the input latched comparators and encode logic to make use of the MOSAIC 3 high performance, highly matched npn tran- sistors provides an excellent speed-power product. In addition, polysilicon resistors which provide very low parasitic capacitance are used as the reference voltage and differential pair loads. The resistor values used in this invention were chosen from available resistors on the array and provide optimum biasing of the differen- tial amplifier transistors, therefore, the resistor values are not critical. Simulations have shown that the circuit can convert a 10 MegaHertz input sine wave into 3 dig- ital bits at a sampling clock frequency of 500 Mega- Hertz. The circuit is implemented on the B15K Transistor Array which features high ft npn transistors, polysilicon

resistors, and a bandgap ref:rence voltage generator for temperature and supply voltage variation compensation.

  The flash converter of Figure 1 has an analog input voltage signal AIN applied' to seven latched compata- tors (detail shown in block~;2 of FIG. 1). The reference voltage input VREFl-VREF7 for each comparator is generated by resistor voltaLe divider ladder network 1, providing reference voltages in one least significant bit increments. When an anal02 signal is applied to the corn- parators, all comparators habg VREFn...