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FASTER PARTIAL REMAINDER FORMATION IN SRT DIVISION

IP.com Disclosure Number: IPCOM000006436D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-03
Document File: 2 page(s) / 121K

Publishing Venue

Motorola

Related People

Paul C. Rossbach: AUTHOR

Abstract

This paper describes a method to improve the per- formance of higher radix SRT dividers built t?om smaller radii blocks. A new partial remainder formation (PRF) circuit for a radix 8 SRT divider is presented which improves the speed at which the next partial remainder is generated. The speed improvement is achieved with no additional cost in silicon area or power consumed. This PRF modification can be. applied to any higher radix SRT divider built from smaller overlapped blocks given the asymmetry of carry-save adders.

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MOTOROLA INC. Technical Developments Volume 15 May 1992

FASTER PARTIAL REMAINDER FORMATION IN SRT DIVISION

by Paul C. Rossbach

ABSTRACT

  This paper describes a method to improve the per- formance of higher radix SRT dividers built t?om smaller radii blocks. A new partial remainder formation (PRF) circuit for a radix 8 SRT divider is presented which improves the speed at which the next partial remainder is generated. The speed improvement is achieved with no additional cost in silicon area or power consumed. This PRF modification can be. applied to any higher radix SRT divider built from smaller overlapped blocks given the asymmetry of carry-save adders.

lNlRODUCTlON

  Higher radix SRT division is a common method of implementing a hardware divider on an arithmetic or general purpose processor. The speed at which proces- sors can perform SRT division is limited by the partial remainder formation (PRF) and the selection of the next quotient bits in the iterative cycles. Since the cost of quo- tient selection (QS) grows exponentially with the radix, higher radix division is often achieved from multiple stages of smaller radix quotient selection blocks. Some improvement in speed can be obtained by overlapping the QS and PFCF logic. An additional improvement in the speed at which the next partial remainder is formed is real&d by reordering the elements of the PRF circuitry

in a higher radix SRT divider built from multiple stages of smaller radix QS blocks. Any speed improvement in a divider's PRF or QS circuitry will result in a significant overall performance improvement since these stages are on the critical path in the iterative cycles of the division. This mod&d PRF circuit can provide for speed enhance- ment to any higher radix divider built from smaller over- lapped blocks given the asymmetry of carry-save adders.

OPERATlON

   A conventional PRF circuit for a radii 8 divider built from three radix 2 stages is shown in Figure 1. The dual "Smux" is a simple 2 to 1 multiplexor that selects the dividend and zero as the starting inputs and the sum

and carry outputs of the ciurent partial remainder dur- ing the iterative cycles. There are three mux/csa pairs before the Master-Slave latch. The muxes input a quo- tient (generated in the QS circuitry) which selects the divisor, the one's complement of the divisor, or zero based on a quotient of -1, 1, or 0 respectively. The csas are carry-save adders that add the selected multiple of the divisor to the previous 'stages sum and carry outputs (an additional "1" is input i'to the least significant carry- save adder's carry input when the one's complement of the divisor is selected to fcmn the two's complement). The new sum outputs are shifted left by one (> >) whi...