Browse Prior Art Database

VIDEO SYSTEM CONTROLLER

IP.com Disclosure Number: IPCOM000006455D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-04
Document File: 3 page(s) / 139K

Publishing Venue

Motorola

Related People

Richard M. Povenmire: AUTHOR

Abstract

This describes a video system controller (VSC) for systems utilizing cathode ray tube (CRT) displays. To display data on a CRT screen requires means for efficient storage, updating and transmission of video data to the CRT The storage medium is typically a dynamic mem- ory array requiring signals controlliig read and write access to the memory array, known as processor request cycles, as well as signals to generate refresh and display update cycles. Display update cycles transfer an entire row of information from the memory array into a shii register which is then clocked to produce one horizon- tal scan line of video data. Refresh cycles are required at certain intervals to recharge the dynamic memory ele- ments. The refresh and display update cycles must occur within a specified period of time while the processor may require access to the memory at any time.

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MOTOROLA INC. Technical Developments Volume 15 May 1992

VIDEO SYSTEM CONTROLLER

by Richard M. Povenmire

  This describes a video system controller (VSC) for systems utilizing cathode ray tube (CRT) displays. To display data on a CRT screen requires means for efficient storage, updating and transmission of video data to the CRT The storage medium is typically a dynamic mem- ory array requiring signals controlliig read and write access to the memory array, known as processor request cycles, as well as signals to generate refresh and display update cycles. Display update cycles transfer an entire row of information from the memory array into a shii register which is then clocked to produce one horizon- tal scan line of video data. Refresh cycles are required at certain intervals to recharge the dynamic memory ele- ments. The refresh and display update cycles must occur within a specified period of time while the processor may require access to the memory at any time.

  In addition to providing control signals directing the aforementioned cycles, the VSC must generate other signals to access data from the shii register or the mem- ory and generate a video data stream in conjunction with the vertical and horizontal sync pulses. A problem lies in arbitrating between the cycle requests and generation of refresh and display update cycles without processor intervention. Processor intervention slows software exe- cution and complicates system sothvare design. The video controller must also provide programmable sync pulse and video data timing to accommodate a large variety of CRTs.

  Referring to Figure 1, cycle request signals on lines 34, 35 and 50 are input to cycle request latch 2, which latches all pending requests via clock signals on line 33. These latched requests are input to priority logic 3, which presents the highest pending request to the video ran-

dom access memory (VRAM) signal generator 4. VRAM signal generator 4 initiates the requested cycle unless another cycle is currently in progress. Requests are prioritized from highest to lowest as follows: display update 50, refresh 35 and processor request 34.

Display update 50 is the highest priority because it must occur during the horizontal blanking period (five

microseconds in length). If any other cycle is being per- formed when the update &cle is requested, the update cycle will be the next request to be granted to insure that it occurs before the end of the horizontal blanking period. Refresh cycle request 35 is second priority

because a refresh cycle must be performed at least once. every ten microseconds. Diiplay update and retmsh cycles are executed in the miniium time possible, allowing the third priority...