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A WAFER LEVEL HOT CARRIER RELlABILlTY SCREENING TEST FOR BIPOLAR TRANSISTORS

IP.com Disclosure Number: IPCOM000006466D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-07
Document File: 3 page(s) / 219K

Publishing Venue

Motorola

Related People

Charles J. Varker: AUTHOR [+3]

Abstract

A major reliability issue for high performance bipo- lar transistors is the reduction of forward current gain (hfe) resulting from hot carrier (HC) generation during operation of the emitter-base pn junction. In BiCMOS curcuits where analog inputs are used to drive bipolar gates such as in digital converters, operational amplii- ers and comparators, the emitter-base junction can be subjected to periodic reverse bias stress which can degrade its operational characteristics.

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MOTOROLA INC. Technical Developments Volume 15

May 1992

A WAFER LEVEL HOT CARRIER RELlAB[LlTY SCREENING TEST FOR BIPOLAR TRANSl$TORS

by Charles J. Varker, Wei-Tsun Shiau and Dave Pettengill

INTRODUCTION AND BACKGROUND

  A major reliability issue for high performance bipo- lar transistors is the reduction of forward current gain (hfe) resulting from hot carrier (HC) generation during operation of the emitter-base pn junction. In BiCMOS curcuits where analog inputs are used to drive bipolar gates such as in digital converters, operational amplii- ers and comparators, the emitter-base junction can be subjected to periodic reverse bias stress which can degrade its operational characteristics.

  Conventional long term reliability testing cannot pro- vide the necessary reliability data needed prior to proc- ess transfer and manufacturing to improve device and process module reliability. A method is needed which can be applied at wafer probe on discrete bipolar test devices early in the development cycle.

Some of the limitations of conventional product reli- ability testing are;

1. It is costly and time consuming requiring fully assembled and packaged product.
2. It produces insufficient lietest data and is often too late for customer needs.
3. It is generally not capable of identifying the causes of reduced reliability.
4. It is not capable of activating all of the relevant failure mechanisms.
5. It has little or no impact on product development and design.

  The approach which is needed is best described as reliability integration (building-in-reliability). This approach relies on understanding and controlling the causes of reduced reliability in devices, processes and manufacturing as opposed to failure rate measurements on product, i.e. proactive reliability as opposed to reac- tive reliability.

Characteristics of reliability integration are;

1. Application of wafer level testing using highly

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accelerated conditions.
2. Line monitors for in-process measurement and control @PC). 1,
3. Identification and control of critical failure mechanisms.
4. Application of reliability-driven design rules derived from tests.
5. Comparative tests which show relative reliability trends.
6. Application of new test methods for fast reliabil- ity screening.

METHOD OF OPERATION

  This disclosure describes a wafer level reliability screening test which uses lebo measurements at a speci- tied voltage as a figure of merit. Calibration of this data is accomplished by periodically using a water level HC stress test to establish the correlation between the time to a specified Hfe degradation level and its prestress lebo. The lebo test method provides a simple nondestructive reliability test which can beiintroduced early in the prod- uct development cycle. It can be used to monitor device and process module design and it provides the data required to develop reliability driven design rules for high reliability product development. This test has been shown to produce...