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ENHANCED FREQUENCY/PERIOD COUNTER

IP.com Disclosure Number: IPCOM000006467D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-07
Document File: 3 page(s) / 150K

Publishing Venue

Motorola

Related People

Thomas J. Hoppal: AUTHOR

Abstract

This publication describes an inexpensive circuit for an enhanced frequency/period counter. Communi- cations analyzers are required to have either a frequency or period counter to make frequency measurements of such signals as the intermediate frequencies (IF), fre- quency error of input signals, modulating signal and tone sequences. These tests require frequency measurements for input signals ranging from 1 Hz to 1 MHz with as much as 0.1 Hz resolution. In particular, tone sequences become very difficult to measure since tone durations can be as short as a few milliseconds. Frequency coun- ters are excellent for measuring high freuency signals while period counters are excellent for measuring low frequency input signals. This circuit performs both func- tions with almost the same hardware, provides a period counter which can measure the frequency of every input cycle and provides 32 bit counters for both frequency and period counting functions.

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MOTOROLA INC. Technical Developments Volume 15 May 1992

ENHANCED FREQUENCY/PERIOD COUNTER

by Thomas J. Hoppal

  This publication describes an inexpensive circuit for an enhanced frequency/period counter. Communi- cations analyzers are required to have either a frequency or period counter to make frequency measurements of such signals as the intermediate frequencies (IF), fre- quency error of input signals, modulating signal and tone sequences. These tests require frequency measurements for input signals ranging from 1 Hz to 1 MHz with as much as 0.1 Hz resolution. In particular, tone sequences become very difficult to measure since tone durations can be as short as a few milliseconds. Frequency coun- ters are excellent for measuring high freuency signals while period counters are excellent for measuring low frequency input signals. This circuit performs both func- tions with almost the same hardware, provides a period counter which can measure the frequency of every input cycle and provides 32 bit counters for both frequency and period counting functions.

divided by two by 12 circuit 4 and both the non-inverted signal 2 and the inverted signal 3 are used by clock and gate selection logic 11. The input signal frequency is divided by two so that non-symmetrical signals can be accurately measured. The clock and input signals on lines 2, 3, 5 and 6 are input to clock and gate selection logic 11, which selects the clocks to be used depending on whether the frequency or period counting function is selected and on the desired resolution. Clock and gate selection logic 11 controls the inputs to counter 0 clock, counter 0 gate and counter 2 gate (lines 8, 9 and 10, respectively) using the algorithm given below.

TABLE I.

Counter circuit input signals for different functions,

  Figure 1 is a schematic diagram of the complete cir- cuit. Timer 18 comprises three sixteen bit counters nec- essary for the frequency/period counting functions. A NEC uPD751054 timer integrated curcuit can be usefully employed as timer 18. Counter 0 of timer 18 is used as the least significant sixteen bits for one of two period counters when in period counter mode. In frequency counter mode, counter 0 is used as the least significant sixteen bits of the frequency counter. Counter 1 is used only in the period counter mode and is used as the least significant sixteen bits ofthe second period counter. Coun- ter 2 of timer 18 is used as the most significant sixteen bits of the frequency counter and as the most signiticant sixteen bits of the period counters.

Mode Res'n. Counter 0 Counter 0 Counter 2 Selected Selected Clock Gate Gate

Period 10 MHz Input12 Input/2 Frequency 0.1 Hz Input 0.1 Hz 0.1 Hz Frequency 1.0 Hz Input l.OHz l.OHz Frequency 10 Hz Input 10Hz 10Hz Frequency 100 Hz Input 100Hz 100Hz

The other clock and gate inputs are fvted as follows:

counter 1 gate: counter 1 clock: counter 2 clock:

Input/2

10 MHz Overtlow from counter 0 or 1.

PERIOD COUNTER OPERATION:...