Browse Prior Art Database

TECHNIQUE FOR IMPLEMENTING A DELAY IN THE T1 TRANSMISSION PATH OF SIMULCAST SYSTEM

IP.com Disclosure Number: IPCOM000006468D
Original Publication Date: 1992-May-01
Included in the Prior Art Database: 2002-Jan-07
Document File: 3 page(s) / 136K

Publishing Venue

Motorola

Related People

Perumal Nathan: AUTHOR

Abstract

In a simulcast system the remote sites are linked to the prime site through digital loop consisting of Tl chan- nel banks and microwave links each having its own path delays. If one of the liiks break the atTected remote site could be reached through alternate path. However the path condition to the affected area will be different and hence it is necessary to optimize the system through Prime Optimization Node (PON) to compensate the amplitude and phase of signals received at the overlap area. The present system has the capability to compen- sate the time delay up to 5.333 milliseconds. But in a large simulcast system with multiple liis this time delay will not be sufficient to compensate for the phase delay. The purpose of Tl delay unit' is to introduce time delay in the Tl path from 1 microsecond to 20 milliseconds in steps of one microsecond. This paper describes the tech- nique in implementing the delay in Tl lime. The delay unit consists of a transformer interface to Tl lime, a Tl repeater to recover data and clock from AMI (Alternate Mark Inversion) line code and the time delay circuit. The receive transformer converts the bipolar AM1 sig- nal to unipolar and the transmit transformer reconstructs the delayed unipolar TTL signal to bipolar AM1 signal for onward transmission.

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MOTOROLA INC. Technical Developmenta Volume 15

May 1992

TECHNIQUE FOR IMPLEMENTING A DELAV IN THE T-l TRANSMISSION PATH OF SIMULCAST $YSTEM

by Perymal Nathan

  In a simulcast system the remote sites are linked to the prime site through digital loop consisting of Tl chan- nel banks and microwave links each having its own path delays. If one of the liiks break the atTected remote site could be reached through alternate path. However the path condition to the affected area will be different and hence it is necessary to optimize the system through Prime Optimization Node (PON) to compensate the amplitude and phase of signals received at the overlap area. The present system has the capability to compen- sate the time delay up to 5.333 milliseconds. But in a large simulcast system with multiple liis this time delay will not be sufficient to compensate for the phase delay. The purpose of Tl delay unit' is to introduce time delay in the Tl path from 1 microsecond to 20 milliseconds in steps of one microsecond. This paper describes the tech- nique in implementing the delay in Tl lime. The delay unit consists of a transformer interface to Tl lime, a Tl repeater to recover data and clock from AMI (Alternate Mark Inversion) line code and the time delay circuit. The receive transformer converts the bipolar AM1 sig- nal to unipolar and the transmit transformer reconstructs the delayed unipolar TTL signal to bipolar AM1 signal for onward transmission.

  The technique involved is to create a gate time equiv- alent to the desired delay time and convert it to a binary word and use the binary word as the address of a ran- dom access memory. Each bit of the recovered data is written in to the memory location of the address which is being updated by decrementing the address on every clock pulse of the recovered clock of Tl lime until the address value reaches zero thereby the data gets delayed by the amount of the binary value set by the gate time. During each clock period of the Tl clock, the memory will read out the content of the address in the first half period and write in the incoming data in the second half period into the same address location. This process con- tinues until a new delay value is set by the gate time. Here the random access memory is organized as a circular queue memory.

Figure 1 shows the elements of the delay circuit.

The' desired delay can be entered through the Binary Coded Decimal (BCD) switches as a decimal value cquiv- alent to the number of microseconds. This value is com- pared to a BCD counter's output which is incremented by a clock of 1 MHz (1 microsecond clock period) when a start/reset (waveform 1) is applied to the binary coun- ter. A logic comparator compares the value of the BCD set by the switches and the content of the BCD counter and issues a logic low if the values do not match and a logic high if the values match. Initially when the start/ reset is applied the comparator issues a logic low (wa...