Browse Prior Art Database

A Packet Formatting Mechanism for RapidIO

IP.com Disclosure Number: IPCOM000006507D
Original Publication Date: 2002-Jan-11
Included in the Prior Art Database: 2002-Jan-11
Document File: 1 page(s) / 32K

Publishing Venue

Motorola

Related People

Srinath Audityan: AUTHOR [+2]

Abstract

This paper discloses a packet formatting mechanism that is area efficient and has minimal logic implementation complexity. The important components of the circuit are: a packet based bus architecture and packet formatting logic to convert internal bus transactions to packet transactions.

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</DIV><DIV>A Packet Formatting Mechanism for RapidIO

Srinath Audityan & Jose M Nunez</DIV><DIV>

Abstract<DIV>

This paper discloses a packet formatting mechanism that is area efficient and has minimal logic implementation complexity. The important components of the circuit are: a packet based bus architecture and packet formatting logic to convert internal bus transactions to packet transactions.<DIV></DIV></DIV><DIV>

Body

The logic complexity and area of packet formatting logic is proportional to the difference in the alignment and size requirements of the internal bus and packet based bus architectures. This circuit solves the logic complexity and area usage problem.