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Browse Prior Art Database

Partial Via-First Dual Inlaid Integration With Buried Etchstop

IP.com Disclosure Number: IPCOM000006508D
Original Publication Date: 2002-Jan-11
Included in the Prior Art Database: 2002-Jan-11
Document File: 1 page(s) / 25K

Publishing Venue

Motorola

Related People

Brad Smith: AUTHOR

Abstract

This invention uses a buried etchstop layer in the via dielectric to provide via bottom size control as well as minimizing the capacitive effects of the etchstop layer.

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Partial Via-First Dual Inlaid Integration With Buried Etchstop

Brad Smith

ABSTRACT

This invention uses a buried etchstop layer in the via dielectric to provide via bottom size control as well as minimizing the capacitive effects of the etchstop layer.

BODY

An extra etchstop layer is added just above the normal via etchstop layer.  The layer labeled “ESL 1” in the picture below can be made as thin as possible, since it’s only function is as a copper barrier.  This minimizes the fringing capacitance of the metal below.  The layer labeled “ESL 2” is where the via etch needs to stop, so it can be a little thicker without affecting the fringing capacitance.

The via etch stops on ESL 2.  Then, when the metal trenches are etched, ESL acts as a hardmask to transfer the via pattern down to ESL 1.  This maintains the correct via size while the portion of the via above ESL 2 is tapered during the trench etch.  Buried hardmasks are often more effective than surface etchstops because they’re shielded from much of the physical ion bombardment that erodes corners.  When the etches are complete, the via bottom is the desired size, with minimal taper, and the upper portion of the via is tapered, which makes filling it easier.