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HIGH-PERFORMANCE SELF-ALIGNED NPN FOR BICMOS

IP.com Disclosure Number: IPCOM000006548D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2002-Jan-14
Document File: 4 page(s) / 183K

Publishing Venue

Motorola

Related People

Robert H. Reuss: AUTHOR [+2]

Abstract

There are a number of methods for fabrication of bipolar transistors within a BiCMOS process. In gen- eral, a CMOS baseline process with only a few added steps to form the bipolar transistor is a preferred approach because of simplicity and compatibility with existing process technology. The emitter-base structure of an NPN device can easily be formed by adding a non-critical, base-implant mask, an emitter-contact mask, and an arsenic-doped-polysilicon emitter layer to a CMOS base- line process. A relatively small amount of incremental process complexity provides a modest performance NPN that significantly adds to the capability of the original CMOS flow. While this procedure for integration of an NPN has been successfully demonstrated (1,2), there are several problems with this method that can result in yield and/or performance limitations. A method to over- come these limitations without losing the overall sim- plicity and ease of integration into CMOS is desirable.

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MOTOROLA INC. Technical Developments Volume 16 August 1992

HIGH-PERFORMANCE SELF-ALIGNED NPN FOR BICMOS

by Robert H. Reuss and Terry Hulseweh

  There are a number of methods for fabrication of bipolar transistors within a BiCMOS process. In gen- eral, a CMOS baseline process with only a few added steps to form the bipolar transistor is a preferred approach because of simplicity and compatibility with existing process technology. The emitter-base structure of an NPN device can easily be formed by adding a non-critical, base-implant mask, an emitter-contact mask, and an arsenic-doped-polysilicon emitter layer to a CMOS base- line process. A relatively small amount of incremental process complexity provides a modest performance NPN that significantly adds to the capability of the original CMOS flow. While this procedure for integration of an NPN has been successfully demonstrated (1,2), there are several problems with this method that can result in yield and/or performance limitations. A method to over- come these limitations without losing the overall sim- plicity and ease of integration into CMOS is desirable.

  The structure of an NPN fabricated by the straight- forward approach described above is shown in Figure 1. From a performance standpoint it is limited because of the large distance between the P+ base-contact region and the edge of the N+ emitter. The connecting region is relatively lightly doped active base (P+ is about 50Q/square, P active base is about 2000CVsquare). The Plink region (between P+ and emitter edge) rather than a P+ implant extending to the N+ junction contributes a large component of base resistance. Both speed and noise performance suffer in devices with high-base resistance. To solve this problem, a method is needed to self-align the P+ and N+ regions to minim& resistance without degradation of other device characteristics. Further, the height to width aspect ratio of the emitter contact is 0.25 or larger. This can lead to an emitter plug and periphery effect (3,4) for poly-emitter devices with this structure as shown in Figure 2. As emitters are scaled below lf~m in width, these effects can have a significant impact on current gain (R). A method to minim& variation in beta with emitter size is needed to extend BiCMOS to submicron geometry. Finally, the emitter contact is formed by etching through 1500-4000A of deposited

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glass. To retain adequate dimensional control reactive ion etching (BIE) is used to open the emitter contact. Tbis introduces a possible yield or reproducibility prob- lem in that BIE processes are well known to induce silicon damage and/or etch into the emitter-base junc- tion area. Described below is a method which over- comes these limitations while at the same time retaining process simplicity and ease of integration into baseline CMOS technology.

  The process flow to solve the above problems is described in Figure 3. No change in the baseline CMOS process is required until after...