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Method for an efficient instruction memory architecture for MIMD-based computing elements

IP.com Disclosure Number: IPCOM000006567D
Publication Date: 2002-Jan-15
Document File: 2 page(s) / 16K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an efficient instruction memory architecture for MIMD-based computing elements. Benefits include improved performance and improved utilization of the chip area devoted to memory.

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Method for an efficient instruction memory architecture for MIMD-based computing elements

Disclosed is a method for an efficient instruction memory architecture for MIMD-based computing elements. Benefits include improved performance and improved utilization of the chip area devoted to memory.

Background


              Conventional computer architectures involve a single execution unit connected to a single instruction memory unit. A known improvement is to equip the instruction memory with a cache function so that code executed most often is more readily accessible. Another known improvement is to take advantage of data parallelism by having a set of execution units executing a common instruction but on different pieces of data simultaneously. This arrangement is referred to as a Single Instruction Multiple Data (SIMD) architecture.

Description

The disclosed method is a concept to switch the memory resource among several processors in a group to allow complex programs to be execute while making efficient use of the memory for the majority of programs that are much smaller. This approach is called the Multiple Instruction, Multiple Data (MIMD) architecture. In this architecture, different instructions are executed in parallel on different pieces of data simultaneously and on different execution units. This architecture is the most flexible but also the most complex to program and build.

              One of the key difficulties with the MIMD approach is allocation of program memory among the separate processor execution units. The pragmatic implementation of the architecture often takes the form of numerous (typically from 16 up to 1024 or more) processing elements that are very similar, if not identical. The base architecture is repeated many times over and any additions to the base architecture are repeated many times over. This can substantially impact items such as die size. In the particular case, consider the instruction memory size. A typical size for local instruction memory is 128 instructions. However, the code size is statistical in nature...