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AC-SCAN: A DESIGN FOR TEST ALTERNATIVE TO BOUNDARY SCAN WHICH ALLOWS DETECTION OF AC SIGNAL FAILURE MODES

IP.com Disclosure Number: IPCOM000006584D
Original Publication Date: 1992-Aug-01
Included in the Prior Art Database: 2002-Jan-16
Document File: 4 page(s) / 227K

Publishing Venue

Motorola

Related People

Michael Beckerle: AUTHOR

Abstract

The AC-Scan technique is described where an AC test signal can be generated by being sent out of a test generator onto any output of a package, and can be observed by an input of a receiving package. A design incorporating this feature allows one to detect AC signal failure modes. This improves upon boundary scan tech- nology because boundary scan allows only the detec- tion of DC failures.

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MOTOROLA INC. Technical Developments Volume 16 August 1992

AC-SCAN: A DESIGN FOR TEST ALTERNATIVE TO BOUNDARY SCAN WHICH ALLOWS DETECTION OF AC SIGNAL FAILURE MODES

by Michael Beckerle

ABSTRACT

  The AC-Scan technique is described where an AC test signal can be generated by being sent out of a test generator onto any output of a package, and can be observed by an input of a receiving package. A design incorporating this feature allows one to detect AC signal failure modes. This improves upon boundary scan tech- nology because boundary scan allows only the detec- tion of DC failures.

1 BACKGROUND AND INTRODUCTION

  Use of boundary scan technology is thought to gen- erally improve the testability of electronic designs. Many people view boundary scan as obviating the need for in-circuit testing (ICT) of circuit boards since the scan path provides the capability to test the connectivity ofthe board's wiring and soldering. Unfortunately, boundary scanning only allows testing the direct current (DC) behavior of a circuit. ICT is traditionally used to deter- mine that the interconnect of a circuit board has the correct electrical characteristics, including both DC and AC response.

  It is possible for a circuit to have failures due to manufacturing defects, handling, or age which are undetectable under DC test, but which affect the AC Characteristics of the circuit. These faults are generally not detectable using boundary scan technology and require use of a logic-analyzer or oscilloscope to debug. New high-density packaging technology doesn't allow ICT or debug via hand-placed probes, such as for a logic analyzer or oscilloscope, unless probe points are specif- ically designed into the device being tested. Examples of this kind of packaging are direct soldered die in multichip modules (the so-called flip-chip package) and pad-array carriers. These techniques are sensitive to bad solder joints due to poor assembly alignment, thermal expan- sion, vibration and a variety of other causes; however, they are unable to be tested for solder joint failures which do not show up as DC boundary scan failures.

0 Motorola. Inc. 1992

  The testing alternative is to use the DUT's inherent capabilities as a circuit to induce particular AC patterns on various outputs. This requires intimate knowledge of the DUT's functionality. Manufacture and test groups often are not familiar enough with the details ofthe com- ponent being tested to make the circuit or device pro- duce appropriate AC signal outputs even when the device can in fact be made to do so.

  This document describes a new technique called AC-Scan which can be viewed as a replacement for in-circuit testing and an enhancement to boundary-scan techniques. The technique provides the ability to create specific AC signal patterns on the output wires of a cir- cuit and to observe these patterns so as to determine if the proper AC signal is received by each input connected to that output. This is done by inc...