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Method to Integrate Pseudo-Random Pattern Generation

IP.com Disclosure Number: IPCOM000006595D
Publication Date: 2002-Jan-16
Document File: 2 page(s) / 28K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for permitting flexible, deterministic, post-silicon testing of microprocessors. The disclosed method allows rapid stimulation of embedded digital circuits (such as cache memories) with a wide variety of stimulus patterns. With the disclosed method, memory-stimulation functionality can be tied to the performance parameters of the chip under test.

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Method to Integrate Pseudo-Random Pattern Generation

Disclosed is a method for permitting flexible, deterministic, post-silicon testing of microprocessors.  The disclosed method allows rapid stimulation of embedded digital circuits (such as cache memories) with a wide variety of stimulus patterns.  With the disclosed method, memory-stimulation functionality can be tied to the performance parameters of the chip
under test.

Traditionally, built-in self-test (BIST) patterns, such as checkerboards and walking ones, are embedded as microcode in integrated circuits (IC).  Traditional BIST patterns are designed to address likely modes of memory failure.  However, these BIST patterns must be designed into the IC before the silicon is laid down.  Thus, designers must know the likely failing stimulus test-patterns for embedded digital circuits before the first silicon for those circuits is laid down.  Because designers must know stimulus test patterns before the silicon is laid down, traditional BIST patterns are often unable to catch failure modes discovered post-silicon in microprocessor memory arrays.

The disclosed method improves post-silicon testing of microprocessor memory structures.  The disclosed method improves testing by using deterministic, pseudorandom pattern-generators (PRPGs) in hardware in host IC designs.  The disclosed method also uses external or internal driving software to control the stimulation of memory arrays through the use of seed test patterns.  The disclosed method’s deterministic pattern-generation circuitry allows precomputation of patterns created by any seed at any pattern-generation step after reset.  Along with host-circuit specifications, the disclosed method allows precomputation of expected results of memory stimulation by seed patterns.

In the disclosed method, the PRPGs stimulate and read back arrays of on-chip memory in order to discover memory marginalities or defects.  In the disclosed method, the PRPGs contain at least one pseudorandom pattern generator.  In the disclosed method, the PRPGs may also be initialized or programmed with seed patterns created by users.  In the disclosed method, the PRPGs may also contain truly random pattern-generation capabilities based on physical principles as well as the deterministic pseudorandom ci...