Browse Prior Art Database

Method for a low cost, self-aligned and bumpless process for IC chip packaging

IP.com Disclosure Number: IPCOM000006608D
Publication Date: 2002-Jan-16
Document File: 4 page(s) / 72K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a low cost, self-aligned and bumpless process for integrated circuit (IC) chip packaging. Benefits include improved throughput and yield from a simplified process, decreased contamination and damage, and improved process extensibility.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 46% of the total text.

Method for a low cost, self-aligned and bumpless process for IC chip packaging  

Disclosed is a method for a low cost, self-aligned and bumpless process for integrated circuit (IC) chip packaging. Benefits include improved throughput and yield from a simplified process, decreased contamination and damage, and improved process extensibility.

Background

              Several conventional approaches exist for bumpless IC die packaging. In the GE method, the die is bonded to a substrate such as a wafer. Dielectric layers are laminated over the substrate. Vias are created by methods such as RIE or laser ablation, followed by established metallization processes such as sputtering and electroplating to create multiple build-up layers. In bumpless build-up layer (BBUL) technology, the die are laminated on a sticky tape and molded to provide encapsulant support that holds the die together. The sticky tape is then removed from the active side, the die surface is cleaned and build-up layers are fabricated over the die surface by using the established processes.

              These approaches suffer from the following yield limiting steps:

·        Maintaining alignment of the die is very difficult, especially during high temperature process steps such as molding and dielectric film curing. Any movement of the die from its original placement makes the alignment of the build-up layer all the more difficult and may even create a fatal defect.

·        Lack of a self-alignment feature makes these existing technologies very difficult for extension to larger die counts. This problem limits throughput, yield, and cost competitiveness.

·        Attachment of any sacrificial layer on the die surface (as in BBUL) increases the potential of die surface contamination. After exposure to a high temperature, layers may leave residue on the die surface that may be very difficult to remove. This contamination may reduce yield.

·        Application of high mechanical forces on the active die surface (such as mold plates with 1000PSI static and dynamic pressure sits over the active side of the chips in BBUL) increases the possibility of cracking or other damage. In conventional approaches, steps such as molding may expose the die surface to high dynamic and static pressures.

General description

              The disclosed method is a process for bumpless packaging of IC chips into a low-inductance package. The process has following attributes:

·        Self-aligned IC chips, ensuring alignment with the build-up layers

·        Bumpless integration into a package

·        No mechanical loading or impact on the active side of the chip

              The key elements of the disclosed method include:

·        Bumpless integration of IC chip into a low inductance, low cost package

·        Self-aligned process for alignment of the chip and the build-up layers

·        Active surface of the IC chip not subjected to any high mechanical pressure/impact

·        Low cost molded V-groove containing template for self-alignment of the IC chips to the build-up layers

·        Thin film build-up technology processes

·        Si back...