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Method for strip-based testing of chip scale packages for stacked die product applications

IP.com Disclosure Number: IPCOM000006615D
Publication Date: 2002-Jan-16
Document File: 3 page(s) / 566K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for strip-based testing of chip scale packages for stacked die product applications. Benefits include improved yield, and reduced cost.

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Method for strip-based testing of chip scale packages for stacked die product applications

Disclosed is a method for strip-based testing of chip scale packages for stacked die product applications.  Benefits include improved yield, and reduced cost.

Background

              Even with 100% wafer sorting, poor logic dice yields (~4-8% failure rates are typical) are not uncommon.  In order to enable various communications chip market segments, a memory die is typically stacked on a logic die.  If the base logic die fails, then the memory die is also lost because the failing dice are not detected until after full package assembly (found at final test). That is, approximately 4-8% of all stacked memory dice (for example, SRAM or Flash memory die which are previously known to be good) are thrown away because they are assembled to a failing logic die.

              This loss is not addressed effectively by a conventional assembly then test flow.  Up until now this type of stacked die yield loss has been tolerated and ignored because of higher profit margins of stacked die logic products.   But due to increasing price pressure for commodity-type communication chip products, which are usually assembled in molded matrix array packaging (MMAP), HD-SCSP, or folded type BGA packaging, these levels of yield loss and added costs are now unacceptable.  Additional test steps (for example, hot sort or other means) may not be cost effective as a test solution, and can sometimes add more total cost than saving provided.

              The conventional assembly test flow for stacked die packaging is:


1.           Sort
2.           Wafer saw
3.           Wafer thinning
4.           First die (logic) attach
5.           Second die (memory) attach
6.           Mold
7.           Ball attach
8.           Singulate
9.           Burn in
10.Class test 1 (logic)
11.         Class test 2 (memory)
12.         Laser mark
13.         FVI
14.         Pack/ship

      All assembly operations up to Singulate are performed in strip-based format. All back-end testing is performed in singulated-unit format.

General description

              The disclosed method is a testing process that applies to various strip packaging formats such as MMAP, HD-SCSP, or folded BGA packaging. The strip testing process is performed on a partially assembled package (with only the logic die attached) with all die locations that have failed being mapped unit by unit on the strip. This strip map is then passed back to the die attach assembly...