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FREQUENCY SYNTHESIZER WITH FINE FREQUENCY RESOLUTION AND NOISE CANCELLATION

IP.com Disclosure Number: IPCOM000006659D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-21
Document File: 2 page(s) / 104K

Publishing Venue

Motorola

Related People

James E. Klekotka: AUTHOR

Abstract

An approach to providing a low-noise RF signal synthesizer having fme frequency resolution and meet- ing the noise performance requirements for a satellite terminal is illustrated in Figure 1. Signals from an,exter- nal reference oscillator are delivered by connections 1 and 2 to frequency dividers 3 and 4, respectively. Divi- sors for hequency dividers 3 and 4 are Rl and R2, respec- tively, where Rl + 1 = R2. Frequencies at 5 and 6 thus are Rl and R2 times the interchannel frequency separa- tion FICFS, providing the desired FICFS. Bandwidths of loops LOOP1 and LOOP2 can be increased by factors Rl and R2, allowing faster loop frequency change, pro- viding improved noise performance and permitting wider drift cancellation loop bandwidth.

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MOTOROLA INC. Technical Developments Volume 17 December 1992

FREQUENCY SYNTHESIZER WITH FINE FREQUENCY RESOLUTION AND NOISE CANCELLATION

by James E. Klekotka

  An approach to providing a low-noise RF signal synthesizer having fme frequency resolution and meet- ing the noise performance requirements for a satellite terminal is illustrated in Figure 1. Signals from an,exter- nal reference oscillator are delivered by connections 1 and 2 to frequency dividers 3 and 4, respectively. Divi- sors for hequency dividers 3 and 4 are Rl and R2, respec- tively, where Rl + 1 = R2. Frequencies at 5 and 6 thus are Rl and R2 times the interchannel frequency separa- tion FICFS, providing the desired FICFS. Bandwidths of loops LOOP1 and LOOP2 can be increased by factors Rl and R2, allowing faster loop frequency change, pro- viding improved noise performance and permitting wider drift cancellation loop bandwidth.

  Fist phase locked loop LOOP1 comprises phase detector 7, loop tilter 25, first voltage controlled oscilla- tor (VCOl) 21, down-conversion mixer 15 and feedback divider 11 having divisor Nl. Second phase locked loop LOOP2 comprises phase detector 8, loop falter 26, sec- ond voltage controlled oscillator (VCO2) 22, down- conversion mixer 16 and feedback divider 12 having divi- sor N2.

  Fist voltge controlled oscillator 21 is coupled via interconnection 31 to bandpass falter 33. Bandpass filter 33 is coupled via lead 35 to mixer 37 having input 39 and output 41. Input 39 is coupled to bandpass tilter 43. Down-conversion mixer 16 is coupled to third voltage controkd oscillator 44 (VCO3). Third voltage controlled oscillator 44 is also coupled to bandpass filter 34 via lead 32. Bandpass Iilter 34 is coupled to mixer 38. Mixer 38 has an input coupled to lead 40 whereby a 45 MHz signal is injected, and has an output coupled to lead 42. Bandpass filters 33, 34 and 43, mixers 38 and 37 and thud voltage controlled oscillator 44 comprise a drill cancellation loop.

LOOP1 and LOOP2 provide a frequency plan:

Four = FVCOI

- Fvcoz - 45 MHz, (1)

where

0 Motorola, 1°C. 1992

F vcci = Fvcoz + (Nl*Fosc)/Rl

and

(2)

Fvox = Fvco, + (N2*Fosc)/R2. (3)

  Here, Four represents the frequenc...