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Browse Prior Art Database

A TRIMMABLE TIME PULSE GENERATOR

IP.com Disclosure Number: IPCOM000006669D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-22
Document File: 2 page(s) / 90K

Publishing Venue

Motorola

Related People

J. H. Norman: AUTHOR

Abstract

This publication describes a digital counter design for systems where minimum clock period phase adjust- ment is required, herein referred to as a Ttimmable Tie Pulse Generator (TTPG).

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MO-LA /NC. Technical Developments Volume 17 December 1992

A TRIMMABLE TIME PULSE GENERATOR

by J. H. Norman

   This publication describes a digital counter design for systems where minimum clock period phase adjust- ment is required, herein referred to as a Ttimmable Tie Pulse Generator (TTPG).

  It is often necessary in digital systems to generate timing pulses off of a high-speed system clock which must be adjusted (synchronized) to some other system reference. This design satisfies the following potential system requirements-

1)Timing chain adjustment in high speed clock period increments, perhaps 20 nS for High Speed CMOS (HSCMOS).

2) Output timing signal advanced or retarded in any multiple of the high-speed clock period.

3) Avoid timing transients by doing large adjustments gradually.

4) Automatic timing fault recovery by a synchro- niziig signal.

  The TTPG is based on a 2-stage ring-tail counter which provides the clock for a normal counter chain, see Figure 1 for a logic diagram. The ring-tail counter normally divides the High Speed Clock (HSCLK) by 4 to provide the System Clock (SCLK) output. When a timing adjustment is required, SCLK is either advanced or retarded by the decoding of the ring-tail counter state

and inverting its input at the appropriate time to cause it to divide by 3 or 5. The number of SCLK's produced during the adjustment period is counted so that the desired amount of adjustment is obtained. Thus with HSCLK at 50 Mhz SCLK is nominally 12.5 Mhz, 16.7 Mhz during an advancing adjustment (trim) and 10 Mhz during a retarding adjustment. For systems which require synchronization of the counter c...