Browse Prior Art Database

MULTI-PILLAR SURROUNDING GATE TRANSISTOR WITH ADVANCED ISOLATION

IP.com Disclosure Number: IPCOM000006677D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-23
Document File: 5 page(s) / 232K

Publishing Venue

Motorola

Related People

Jon Fitch: AUTHOR [+2]

Abstract

The conventional planar MOSFET with LOCOS type isolation suffers from two problems with respect to scalability: (1) the scalability of the MOSFET is limited by short channel effects and by the minimum resolva- ble feature size of present day photolithography tools, and (2) lateral encroachment into the active area is a limiting factor for LOCOS and LOCOS-lie isolation schemes, and (3) the device density on an IC is limited by the minimum area required to construct a MOSFET which is roughly 10 times the square of the minimum feature size, i.e. lOF2. Thus, the scalability of the con- ventional MOSFET is limited and the down sizing of device dimensions may not be enough to meet future scaling requirements.

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0 M MO-LA

INC. Technical Developments Volume 17 December 1992

MULTI-PILLAR SURROUNDING GATE TRANSISTOR WITH ADVANCED ISOLATION

by Jon Fitch and Carlos Mazur6

DEFINITION OF PROBLEM

  The conventional planar MOSFET with LOCOS type isolation suffers from two problems with respect to scalability: (1) the scalability of the MOSFET is limited by short channel effects and by the minimum resolva- ble feature size of present day photolithography tools, and (2) lateral encroachment into the active area is a limiting factor for LOCOS and LOCOS-lie isolation schemes, and (3) the device density on an IC is limited by the minimum area required to construct a MOSFET which is roughly 10 times the square of the minimum feature size, i.e. lOF2. Thus, the scalability of the con- ventional MOSFET is limited and the down sizing of device dimensions may not be enough to meet future scaling requirements.

PRIOR ART

  The multi-pillar surrounding gate transistor (M-SGT) has already been proposed by Nitayama et. al. [ 11. The basic unit of the M-SGT is a pillar shaped vertical MOSFET. To make the M-SGT many of these vertical pillar shaped MOSFETs are connected together in par- allel. The resulting structure occupies only a fraction of the area of a conventional MOSFET with the same cur- rent driveability. In Nitayama's embodiment, no isola- tion scheme is specified.

  Hisamoto et. al. 121 has proposed an advanced iso- lation scheme which creates thin blades of silicon float- ing on field oxide. These blades may be attached to the substrate or they may be SOI. This is accomplished by etching a thin blade of silicon from the substrate, cap- ping the top and sides of the blade with silicon nitride, and performing a field oxidation step which selectively oxides the areas which aren't capped with nitride. Hisamoto makes use of the lateral oxidation compo- nent to use the bid's beak to encroach underneath the silicon pillar.

INVENTION AND PROBLEM SOLLKION

  The invention we propose is a multi-pillar surround- ing gate transistor (M-SGT) constructed with either of two advanced isolation schemes: (a) non-SO1 negative encroachment isolation, and (b) full SO1 isolation. One should note that the same fabrication scheme used for the M-SGT could also be used for a vertical MOSFET if only one seed pillar was formed and one channel was grown or even a conventional planar MOSFET The proc- ess flow is as follows:

(1) Deposit a thin layer of oxide (a pad oxide to avoid depositing nitride on silicon), followed by a thicker layer of nitride (which will later serve as part of the mask for the selective oxidation), followed by a layer of TEOS of comparable thickness to the nitride (this is the masking layer for etching the silicon pillars because present day etch processes have very good selectivity of silicon to oxide).

(2) Pattern and etch the oxide/nitride/oxide layer so that small circular islands remain. Using these islands as a mask, etch silicon pillars from of the substrate.

(3...