Browse Prior Art Database

UNDERGATED TFTS WITH P + POLY/TiN GATES

IP.com Disclosure Number: IPCOM000006678D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-23
Document File: 2 page(s) / 105K

Publishing Venue

Motorola

Related People

Frank K. Baker: AUTHOR [+4]

Abstract

Static RAMS with densities of 16Mb or more will require polysilicon PMOS thin-film transistor (TFT) loads in order to control standby current, improve the soft error rate, overcome diode leakage problems, and allow supply voltage scaling. The most ,common implementa- tion of the TFT load involves forming a pair of polysilicon gate electrodes, which attach to the SRAM data storage nodes, and then forming polysilicon channels which run across the top of each gate electrode, separated from the underlying gates by only a thin TFT dielectric. This is known as the "undergated" approach to TFT fabrica- tion. The technique described below utilizes TiN and p+ doped polysilicon to form the TFT gate electrodes. This choice of materials provides optimum intercon- nection between the various portions of the TFT load devices, without compromising the quality of the TFf dielectric.

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MOmOLA INC. Technical Developments 'Volume 17 December 1992

UNDERGATED TFTS WITH P + POLY/TiN GATES

by Frank K. Baker, Thomas McNelly, A. R. Sitaram and BichYen Nguyen

I. ABSTRACT

  Static RAMS with densities of 16Mb or more will require polysilicon PMOS thin-film transistor (TFT) loads in order to control standby current, improve the soft error rate, overcome diode leakage problems, and allow supply voltage scaling. The most ,common implementa- tion of the TFT load involves forming a pair of polysilicon gate electrodes, which attach to the SRAM data storage nodes, and then forming polysilicon channels which run across the top of each gate electrode, separated from the underlying gates by only a thin TFT dielectric. This is known as the "undergated" approach to TFT fabrica- tion. The technique described below utilizes TiN and p+ doped polysilicon to form the TFT gate electrodes. This choice of materials provides optimum intercon- nection between the various portions of the TFT load devices, without compromising the quality of the TFf dielectric.

II. STATEMENT OF THE PROBLEM

  The TFT loads in an SRAM cell are typically p-channel devices, while the underlying bulk devices are typically n-channel. Unfortunately, this means that an unwanted p/n junction will form where the drain of the TFT load and the drain of the bulk pull-down device come together. This p/n junction causes a voltage drop which reduces the level of stored data in the cell, nearly eliminating the advantages offered by the TFT load.

  Several techniques have been proposed to form an ohmic contacts in place of the p/n junction. The most common method involves using n+ doped polysilicon to form the TFI gate electrode. This n+ polysilicon layer can easily make ohmic contact to the n+ doped drain of the bulk pull-down transistor. A refractory metal, such as Tii, can be formed on top of then+ polysilicon TFT gate. If the overlying p-type TFT channel poly is then

connected to the Tii, the p-poly/Tii/n-poly stack forms a low resistance, nearly ohmic contact. However, a h...