Browse Prior Art Database

Multi-Processor Debug Interface

IP.com Disclosure Number: IPCOM000006692D
Original Publication Date: 2002-Jan-23
Included in the Prior Art Database: 2002-Jan-23
Document File: 5 page(s) / 48K

Publishing Venue

Motorola

Related People

Joseph C. Circello: AUTHOR [+3]

Abstract

Today's System-On-A-Chip (SoC) designs need embedded processors with sophisticated debug and monitoring logic to aid in the design, debug and performance analysis of the system solution. Such processors may include Real-Time Trace, Background Debug, and Real-Time Debug support.

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Multi-Processor Debug Interface

By Joseph C. Circello, Daniel M. McCarthy and Sheilah Phan

Abstract

Today's System-On-A-Chip (SoC) designs need embedded processors with sophisticated debug and monitoring logic to aid in the design, debug and performance analysis of the system solution. Such processors may include Real-Time Trace, Background Debug, and Real-Time Debug support.

Furthermore, today's SoC solutions are employing multi-processor designs to meet the growing needs of processing power, bandwidth, and functionality. In this type of multi-processor integrated solution, it is necessary for an external development system (often known as an emulator) to be able to communicate, control, and receive output from any processor. These processors may be deeply embedded and run at different and higher frequencies than the chip pins.

The Solution

The solution detailed here provides a shared debug interface in the SoC, external to the processors, that provides real-time and background support of all the processors through a single physical interface. The single physical debug port is logically connected to one processor at a time and may be switched among processors. Every processor provides synchronous information at the completion of each debug command. All synchronization among the various processors is handled at speed in an efficient, high throughput full-duplex mode serial interface.  SoC designs often embed high frequency processors far from the external chip pin interfaces with multiple clock domains among the processors. Unique debug interfaces per processor are expensive, hard to control, and hard to synchronize. The unified debug interface provided by this approach minimizes cost and removes synchronization problems while providing feature-rich debug environment.


Detailed Description

The Multi-Processor Debug Interface unit has a single shared debug interface to the chip pins plus a debug interface to every processor in the SoC. For example, this interface may have five control/serial data pins plus an 8-bit parallel output bus for processor status and data to external emulator systems. The debug interface supports the following functions:

1.       Real-Time Trace Support

This provides the ability to determine the dynamic execution path through an application. For example, one solution implements an 8-bit parallel output bus which provides information on processor execution status and data to an external emulator system. Using this status and data information along with the memory image, the exact dynamic execution path can be determined.

2.       Background Debug Mode (BDM)

This provides low-level debugging in the processor core. In BDM, the processor is halted and a variety of commands can be sent to the processor to access memory and registers. The communication with the external emulator uses a 3-pin, serial full-duplex channel.

3.       Real-Time Debug Support

In many real-time embedded applications, the processor cannot be halted. Therefore, a proces...