Browse Prior Art Database

Mechanism to Optimize DMA Read & Write Transfers

IP.com Disclosure Number: IPCOM000006693D
Original Publication Date: 2002-Jan-23
Included in the Prior Art Database: 2002-Jan-23
Document File: 2 page(s) / 42K

Publishing Venue

Motorola

Related People

Srinath Audityan: AUTHOR [+3]

Abstract

This proposes a method and apparatus for optimizing direct memory access (DMA) read papers & write transfers of different sizes to maximize system buffer utilization thereby improving the DMA performance. The important components of this idea are: a system having interfaces with different size and alignment requirements, a DMA controller that has separate source and destination controls to transfer data among all interfaces, a hardware managed static buffer allocation scheme to simplify the buffer management control logic, and a buffer pool that is shared by read & write transfers of all DMA channels.

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Mechanism to Optimize DMA Read & Write Transfers</DIV><DIV>

Srinath Audityan, </DIV><DIV>Jose M Nunez & </DIV><DIV>Marie J Sullivan

Abstract</DIV><DIV>

This proposes a method and apparatus for optimizing direct memory access (DMA) read papers & write transfers of different sizes to maximize system buffer utilization thereby improving the DMA performance. The important components of this idea are:  </DIV><DIV>a system having interfaces with different size and alignment requirements, a DMA controller that has separate source and destination controls to transfer data among all interfaces, a hardware managed static buffer allocation scheme to simplify the buffer management control logic, and a buffer pool that is shared by read & write transfers of all DMA channels.

Body 

A DMA transfer is split across single or multiple read and single or multiple write transfers. The number of reads and writes for a DMA transfer are the same in an ideal case. But this is not the case when there are different interfaces with different size and alignment requirements. A single large DMA read may be able to satisfy multiple small DMA writes and multiple small DMA reads may be needed to satisfy a large DMA write. Existing buffer management mechanisms are not efficient for the non-ideal case and this has an impact on the DMA performance. This idea proposes a mechanism that utilizes the system buffering resources efficiently thereby significantly boosting the DMA performance.

 </DIV></DIV><DIV>A signed...