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SONOS Flash EEPROM Enhanced Programming Scheme Using a Si1-xGex Layer

IP.com Disclosure Number: IPCOM000006698D
Original Publication Date: 2002-Jan-23
Included in the Prior Art Database: 2002-Jan-23
Document File: 4 page(s) / 75K

Publishing Venue

Motorola

Related People

Chi-Nan Brian Li: AUTHOR

Abstract

The programming of floating gate based Non-Volatile Memory (NVM) cells using Hot Carrier Injection (HCI) programming has been main stream in the semiconductor industry for the last decade. The problem with scalability of the tunnel oxide has limited the operating voltages in flash bitcell programming. Off state column leakage in a selected column during HCI programming has also limited device scaling due to short channel effects. Recently, a back biased programming scheme has been proposed for the next generation flash (electrically erasable programmable read only memory) EEPROM programming, reducing the column leakage by increasing the effective bitcell threshold voltage, which in turn reduce the column leakage during programming.[1] At the same time, simulation work has shown that the Si1-xGex/Si substrate can increase the back-bias programming efficiency. [2] In this disclosure, a flash EEPROM NVM bitcell using (oxide-nitride-oxide) ONO as the charge storage region on a Si/Si1-xGex substrate using back bias programming scheme is proposed.

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SONOS Flash EEPROM Enhanced Programming Scheme Using a Si1-xGex Layer

Chi-Nan Brian Li

Abstract

The programming of floating gate based Non-Volatile Memory (NVM) cells using Hot Carrier Injection (HCI) programming has been main stream in the semiconductor industry for the last decade.  The problem with scalability of the tunnel oxide has limited the operating voltages in flash bitcell programming.  Off state column leakage in a selected column during HCI programming has also limited device scaling due to short channel effects.  Recently, a back biased programming scheme has been proposed for the next generation flash (electrically erasable programmable read only memory) EEPROM programming, reducing the column leakage by increasing the effective bitcell threshold voltage, which in turn reduce the column leakage during programming.[1]   At the same time, simulation work has shown that the Si1-xGex/Si substrate can increase the back-bias programming efficiency. [2]  In this disclosure, a flash EEPROM NVM bitcell using (oxide-nitride-oxide) ONO as the charge storage region on a Si/Si1-xGex substrate using back bias programming scheme is proposed.

Body

The back bias programming scheme utilizes the secondary electron generated in the channel region to charge up the floating gate in a floating gate based NVM device, accomplishing the programmed (or High Vt) operation [1].  The primary impact ionization from the channel hot carriers in a NMOS flash with a P-type substrate generates electron/hole pairs at the drain region as shown in Figure 1.  Because the substrate bias is at negative potential, the hole from the generated electron/hole pair drifts along the channel region and creates a secondary electron.  Due to the secondary electron generation, a third body effect, the programming occurs at the channel region with less operating voltage requirements.  The secondary electron is then subject to a vertical electric field which is formed by the positive gate voltage and negative well potential.  The secondary electron is then attracted to the floating poly gate by jumping over the oxide/Si potential barrier, and the device threshold voltage is changed due to the negative charge stored in the floating gate.   The state is normally referred to as the programmed state.  As shown in  REF _Ref534623524 \h Figure 2, the programming efficiency can further be improved by incorporating a Si1-xGex/Si strained layer substrate in the floating gate based NVM device [2][3].  The lowered band gap of the Si1-xGex can improve the generation rate of the secondary electron in the channel region.  Therefore, the programming efficiency is improved with higher programming speed.  The problem associated with these solutions is that the manufacturing process to form a floating gate is complex and costly.  To improve the process simplicity, an alternative flash structure utilizing ONO as the storage region has been proposed by Lancaster et al. [4] , as shown in Figure 3. This solution is to rep...