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AN OTP EPROM BUILT WITH A 1T FLASH EEPROM CORE

IP.com Disclosure Number: IPCOM000006713D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-24
Document File: 2 page(s) / 133K

Publishing Venue

Motorola

Related People

Ko-Min Chang: AUTHOR [+3]

Abstract

Microcontrollers (MC&) thrive on the ability to be integrated with an assortment of non-volatile memories (NVMs). Typically, a large array of read-only memory (ROM) is needed for control code storage and a small array of full-featured electrically-erasable programmable ROM (EEPROM) is used for frequently-updated data storage. Due to its long torn-around time, ROMs are usually being emulated by the low-cost one-time programmable (OTP) electrically progmmmable ROMs (EPROMs). While OTP EPROMs require devices that can handle - 12V, full-featured EEPROMs require dif- ferent devices that can handle -20V and a high quality thin tunnel oxide. Although the availabiity of an assort- ment of NVMs on one chip is highly desirable, the real- ization of such requires a strong base of mixed technol- ogy. A new addition to the NVM family is the flash EEPROM. With its small cell size as the OTP EPROM and its electrical erasability as the full-featured EEPROM, flash EEPROM becomes the best compromise for den- sity and flexibility. However, for low-cost user- programmable applications, OTP EPROM is still the choice. It is the purpose of this article to describe the idea of achieving the OTP EPROM cost/bit perform- ance by building it with a one-transistor (1T) flash EEPROM core in a mixed technology environment.

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M-LA INC. Technical Developments Volume 17 December 1992

AN OTP EPROM BUILT WITH A 1T FLASH EEPROM CORE

by Ko-Min Chang, Shih K. Cheng, and Clinton Kuo

INTRODUCTION

  Microcontrollers (MC&) thrive on the ability to be integrated with an assortment of non-volatile memories (NVMs). Typically, a large array of read-only memory (ROM) is needed for control code storage and a small array of full-featured electrically-erasable programmable ROM (EEPROM) is used for frequently-updated data storage. Due to its long torn-around time, ROMs are usually being emulated by the low-cost one-time programmable (OTP) electrically progmmmable ROMs (EPROMs). While OTP EPROMs require devices that can handle - 12V, full-featured EEPROMs require dif- ferent devices that can handle -20V and a high quality thin tunnel oxide. Although the availabiity of an assort- ment of NVMs on one chip is highly desirable, the real- ization of such requires a strong base of mixed technol- ogy. A new addition to the NVM family is the flash EEPROM. With its small cell size as the OTP EPROM and its electrical erasability as the full-featured EEPROM, flash EEPROM becomes the best compromise for den- sity and flexibility. However, for low-cost user- programmable applications, OTP EPROM is still the choice. It is the purpose of this article to describe the idea of achieving the OTP EPROM cost/bit perform- ance by building it with a one-transistor (1T) flash EEPROM core in a mixed technology environment.

ATTBIBLmS OF OTF' EPROM

  The key factor that the OTP EPROM remains to be the prime candidate for ROM emulation lies in its low cost per bit performance. The compact 1T stacked- gate coniiguration permits a high-density NVM array be built with relatively small real estate of silicon. Elec- trically, the -12V operating voltage does not require large isolation distances as the full-featured EEPROM does and the l.SV, nominal, erased-threshold voltage (Vte) allows the fast access of the memory contents.

  End users are expected to program the memory con- tent only once because the die is housed in a plastic package, which is another reason for low overall cost.

8 Motomla. Inc. ,992

The use of plastic package, however, prevents any final test on programming from being conducted due to the fact that no UV erasure can be performed on the pack- aged parts. This poses as a major draw back of the OTP EPROM. Parts can now only be tested at unit probe on wafer with no sophisticated test patterns such as checker board, reverse checker board, and diagonals to weed out latent defects. Wafers will have to be W erased between tests in order for those patterns be performed, which means longer test time and higher test cost. In addition, the detrimental effects of assembly such as die attachment, wire bond, and plastic molding on program- mmg characteristics can not be screened out.

ATTRIBUTES OF 1T FLASH EEPROM

  1T Flash EEPROM, on the other hand, has a slightly larger (- 10%) cell size but can be progr...