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IMPROVED ECL DECODING AND LEVEL CONVERSION CIRCUIT

IP.com Disclosure Number: IPCOM000006715D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-24
Document File: 1 page(s) / 49K

Publishing Venue

Motorola

Related People

Ruey J. Yu: AUTHOR [+2]

Abstract

The figure that follows shows a conversion circuit, which can take ECL level inputs, perform NOR logic function, and then provide 'ITL output drivability. Devices Ml and M2 perform logic functions while M3, M6, and M7 perform the necessary level translation.

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INC. Technical Developments Volume 17 December1992

IMPROVED ECL DECODING AND LEVEL CONVERSION CIRCUIT

by Ruey J. Yu and Karl L. Wang

   The !igure that follows shows a conversion circuit, which can take ECL level inputs, perform NOR logic function, and then provide 'ITL output drivability. Devices Ml and M2 perform logic functions while M3, M6, and M7 perform the necessary level translation.

  During the SELECT mode, output OUT is TTL logic high when both In1 and In2 are ECL logic low. During the DESELECT mode, output OUT is TTL logic low when In1 or In2 is ECL logic high. For this circuit to be of any practical usage, the difference in speed between the SELECT and DESELECT modes should be minimal. If there is any speed difference, the DESELECT mode should be faster than the SELECT mode over a desired power supply range.

  The features of this circuit are twofold. Fist, the constant current source, which is provided by M7 gated by PBIAS referencing to VDD, enables this circuit to have rather uniform SELECT and DESELECT speeds over a wide power supply range. Second, the feedback loop provided by M4 and MS enables the output OUT to activate M4 and MS that have the effect of speeding up the discharge of node NlOl. In short, the feedback mechanism is only engaged when the circuit is switching from the SELECT mode to the DESELECT mode. All these features make this circuit practical and can per- form all the expected functions with maximal speed and minimal power ov...