Browse Prior Art Database

ON-CHIP EMULATION (OnCE) USING MEMORY MAPPED REGISTERS

IP.com Disclosure Number: IPCOM000006716D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2002-Jan-24
Document File: 3 page(s) / 175K

Publishing Venue

Motorola

Related People

Yoav Talgam: AUTHOR [+3]

Abstract

Traditionally, microprocessor based systems were debugged using an In-Circuit-Emulator (ICE)+ device that is attached to the microprocessor socket (some- times replacing it), which, under operator control exe- cutes either the normal application software or special debug software, halting execution when specific events occur or when manually requested to do so by the oper- ator and providing the operator with internal micropro- cessor status (such as register states) or system statis (such as memory or I/O state).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 38% of the total text.

Page 1 of 3

0 M

MC7WRCLA INC. Technical Developments Volume 17 December 1992

ON-CHIP EMULATION (OnCE) USING MEMORY MAPPED REGISTERS

by Yoav Talgam, llan Pardo, and Israel Kashat

  Traditionally, microprocessor based systems were debugged using an In-Circuit-Emulator (ICE)+ device that is attached to the microprocessor socket (some- times replacing it), which, under operator control exe- cutes either the normal application software or special

debug software, halting execution when specific events occur or when manually requested to do so by the oper- ator and providing the operator with internal micropro- cessor status (such as register states) or system statis (such as memory or I/O state).

  A system instrumented with an ICE must be 100% functional and work with the same electrical parameters of the original system. This is a diicult task-especially with modem highly integrated microprocessors, unless the VLSI microprocessor emulates itself. Other solu- tions take extra time, cost and risk to develop. However, integration of internal acceleration schemes such as caches and speculative execution hides the internal activities from the external microprocessor interface. Therefore, the ICE hardware may not have sufficient information on the processor state to cause execution to halt on events of interest. Also, some of the system elements under debug, such as serial interfaces, may be integrated onto the microprocessor and uncontrollable from external ICE circuitry. Finally, as VLSI microprocessors become more powerhrl they possess wider buses and operate at higher bus speeds and with tighter bus protocols. Attaching an external ICE to a microprocessor may be mechanically or electrically infeasible, especially for in-field work.

  A solution is to integrate the ICE facility itself onto the microprocessor chip. It is desired that al1 micropro- cessors integrate this facility such that all deployed sys- tem can be debugged and to avoid inventory problems. However, since the debug feature is only used in a small fraction of the product life, its inclusion must not effect the product cost. Therefore, On-Chip Circuit EmuIa- tion (OnCE) must be implemented in an extremely area efficient way. For the same reason, it must interface to the operator without increasing the pin count; yet it can not be multiplexed with other operational chip functions such that debuggability of all deployed systems is assured

0 Motorola. 1°C. ,992

  To meet these design constraints, our approach is using minhnum amount of hardware to implement serial con- nection between the microprocessor ICE facility and the operator console, and implementing all debug oper- ations via software which is run on the target micropro- cessor itself. Further, we do not require a debug mode- hence debug software features (such as register dumps, memory checksums, peripheral self-tests, etc.) may be programmed just like ordinary software and executed from the target system memory at full processor per-...